URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_1024x32_bw.v] - Diff between revs 142 and 258

Rev 142	Rev 258
Line 532...	Line 532...
`//`	`//`
`// RAM address register`	`// RAM address register`
`//`	`//`
`always @(posedge clk or posedge rst)`	`always @(posedge clk or posedge rst)`
`if (rst)`	`if (rst)`
`addr_reg <= #1 10'h000;`	`addr_reg <= 10'h000;`
`else if (ce)`	`else if (ce)`
`addr_reg <= #1 addr;`	`addr_reg <= addr;`

`//`	`//`
`// RAM write byte 0`	`// RAM write byte 0`
`//`	`//`
`always @(posedge clk)`	`always @(posedge clk)`
`if (ce && we[0])`	`if (ce && we[0])`
`mem_0[addr] <= #1 di[7:0];`	`mem_0[addr] <= di[7:0];`

`//`	`//`
`// RAM write byte 1`	`// RAM write byte 1`
`//`	`//`
`always @(posedge clk)`	`always @(posedge clk)`
`if (ce && we[1])`	`if (ce && we[1])`
`mem_1[addr] <= #1 di[15:8];`	`mem_1[addr] <= di[15:8];`

`//`	`//`
`// RAM write byte 2`	`// RAM write byte 2`
`//`	`//`
`always @(posedge clk)`	`always @(posedge clk)`
`if (ce && we[2])`	`if (ce && we[2])`
`mem_2[addr] <= #1 di[23:16];`	`mem_2[addr] <= di[23:16];`

`//`	`//`
`// RAM write byte 3`	`// RAM write byte 3`
`//`	`//`
`always @(posedge clk)`	`always @(posedge clk)`
`if (ce && we[3])`	`if (ce && we[3])`
`mem_3[addr] <= #1 di[31:24];`	`mem_3[addr] <= di[31:24];`


`endif // !OR1200_XILINX_RAMB16	`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4	`endif // !OR1200_XILINX_RAMB4
`endif // !OR1200_VIRTUALSILICON_SSP	`endif // !OR1200_VIRTUALSILICON_SSP