OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_1024x8.v] - Diff between revs 10 and 142

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 10 Rev 142
Line 61... Line 61...
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: or1200_spram_1024x8.v,v $
 
// Revision 2.0  2010/06/30 11:00:00  ORSoC
 
// Minor update: 
 
// Coding style changed.
 
//
 
// Revision 1.9  2005/10/19 11:37:56  jcastillo
 
// Added support for RAMB16 Xilinx4/Spartan3 primitives
 
//
// Revision 1.8  2004/06/08 18:15:32  lampret
// Revision 1.8  2004/06/08 18:15:32  lampret
// Changed behavior of the simulation generic models
// Changed behavior of the simulation generic models
//
//
// Revision 1.7  2004/04/05 08:29:57  lampret
// Revision 1.7  2004/04/05 08:29:57  lampret
// Merged branch_qmem into main tree.
// Merged branch_qmem into main tree.
Line 274... Line 281...
//
//
// Block 0
// Block 0
//
//
RAMB4_S4 ramb4_s4_0(
RAMB4_S4 ramb4_s4_0(
        .CLK(clk),
        .CLK(clk),
        .RST(rst),
        .RST(1'b0),
        .ADDR(addr),
        .ADDR(addr),
        .DI(di[3:0]),
        .DI(di[3:0]),
        .EN(ce),
        .EN(ce),
        .WE(we),
        .WE(we),
        .DO(doq[3:0])
        .DO(doq[3:0])
Line 287... Line 294...
//
//
// Block 1
// Block 1
//
//
RAMB4_S4 ramb4_s4_1(
RAMB4_S4 ramb4_s4_1(
        .CLK(clk),
        .CLK(clk),
        .RST(rst),
        .RST(1'b0),
        .ADDR(addr),
        .ADDR(addr),
        .DI(di[7:4]),
        .DI(di[7:4]),
        .EN(ce),
        .EN(ce),
        .WE(we),
        .WE(we),
        .DO(doq[7:4])
        .DO(doq[7:4])
Line 309... Line 316...
// Added By Nir Mor
// Added By Nir Mor
//
//
 
 
RAMB16_S9 ramb16_s9(
RAMB16_S9 ramb16_s9(
        .CLK(clk),
        .CLK(clk),
        .SSR(rst),
        .SSR(1'b0),
        .ADDR({1'b0,addr}),
        .ADDR({1'b0,addr}),
        .DI(di),
        .DI(di),
        .DIP(1'b0),
        .DIP(1'b0),
        .EN(ce),
        .EN(ce),
        .WE(we),
        .WE(we),

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.