URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_128x32.v] - Diff between revs 258 and 358

Rev 258	Rev 358
Line 262...	Line 262...
`assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};`	`assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};`

`//`	`//`
`// RAM address register`	`// RAM address register`
`//`	`//`
`always @(posedge clk or posedge rst)`	always @(posedge clk or `OR1200_RST_EVENT rst)
`if (rst)`	if (rst == `OR1200_RST_VALUE)
`addr_reg <= {aw{1'b0}};`	`addr_reg <= {aw{1'b0}};`
`else if (ce)`	`else if (ce)`
`addr_reg <= addr;`	`addr_reg <= addr;`

`//`	`//`