URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_2048x32.v] - Diff between revs 10 and 142

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Rev 10	Rev 142
Line 61...	Line 61...
`//// ////`	`//// ////`
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: or1200_spram_2048x32.v,v $`
	`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
	`// Minor update:`
	`// Coding style changed.`
	`//`
	`// Revision 1.10 2005/10/19 11:37:56 jcastillo`
	`// Added support for RAMB16 Xilinx4/Spartan3 primitives`
	`//`
`// Revision 1.9 2004/06/08 18:15:32 lampret`	`// Revision 1.9 2004/06/08 18:15:32 lampret`
`// Changed behavior of the simulation generic models`	`// Changed behavior of the simulation generic models`
`//`	`//`
`// Revision 1.8 2004/04/05 08:29:57 lampret`	`// Revision 1.8 2004/04/05 08:29:57 lampret`
`// Merged branch_qmem into main tree.`	`// Merged branch_qmem into main tree.`
Line 277...	Line 284...
`//`	`//`
`// Block 0`	`// Block 0`
`//`	`//`
`RAMB4_S2 ramb4_s2_0(`	`RAMB4_S2 ramb4_s2_0(`
`.CLK(clk),`	`.CLK(clk),`
`.RST(rst),`	`.RST(1'b0),`
`.ADDR(addr),`	`.ADDR(addr),`
`.DI(di[1:0]),`	`.DI(di[1:0]),`
`.EN(ce),`	`.EN(ce),`
`.WE(we),`	`.WE(we),`
`.DO(doq[1:0])`	`.DO(doq[1:0])`
Line 290...	Line 297...
`//`	`//`
`// Block 1`	`// Block 1`
`//`	`//`
`RAMB4_S2 ramb4_s2_1(`	`RAMB4_S2 ramb4_s2_1(`
`.CLK(clk),`	`.CLK(clk),`
`.RST(rst),`	`.RST(1'b0),`
`.ADDR(addr),`	`.ADDR(addr),`
`.DI(di[3:2]),`	`.DI(di[3:2]),`
`.EN(ce),`	`.EN(ce),`
`.WE(we),`	`.WE(we),`
`.DO(doq[3:2])`	`.DO(doq[3:2])`
Line 303...	Line 310...
`//`	`//`
`// Block 2`	`// Block 2`
`//`	`//`
`RAMB4_S2 ramb4_s2_2(`	`RAMB4_S2 ramb4_s2_2(`
`.CLK(clk),`	`.CLK(clk),`
`.RST(rst),`	`.RST(1'b0),`
`.ADDR(addr),`	`.ADDR(addr),`
`.DI(di[5:4]),`	`.DI(di[5:4]),`
`.EN(ce),`	`.EN(ce),`
`.WE(we),`	`.WE(we),`
`.DO(doq[5:4])`	`.DO(doq[5:4])`
Line 316...	Line 323...
`//`	`//`
`// Block 3`	`// Block 3`
`//`	`//`
`RAMB4_S2 ramb4_s2_3(`	`RAMB4_S2 ramb4_s2_3(`
`.CLK(clk),`	`.CLK(clk),`
`.RST(rst),`	`.RST(1'b0),`
`.ADDR(addr),`	`.ADDR(addr),`
`.DI(di[7:6]),`	`.DI(di[7:6]),`
`.EN(ce),`	`.EN(ce),`
`.WE(we),`	`.WE(we),`
`.DO(doq[7:6])`	`.DO(doq[7:6])`
Line 329...	Line 336...
`//`	`//`
`// Block 4`	`// Block 4`
`//`	`//`
`RAMB4_S2 ramb4_s2_4(`	`RAMB4_S2 ramb4_s2_4(`
`.CLK(clk),`	`.CLK(clk),`
`.RST(rst),`	`.RST(1'b0),`
`.ADDR(addr),`	`.ADDR(addr),`
`.DI(di[9:8]),`	`.DI(di[9:8]),`
`.EN(ce),`	`.EN(ce),`
`.WE(we),`	`.WE(we),`
`.DO(doq[9:8])`	`.DO(doq[9:8])`
Line 342...	Line 349...
`//`	`//`
`// Block 5`	`// Block 5`
`//`	`//`
`RAMB4_S2 ramb4_s2_5(`	`RAMB4_S2 ramb4_s2_5(`
`.CLK(clk),`	`.CLK(clk),`
`.RST(rst),`	`.RST(1'b0),`
`.ADDR(addr),`	`.ADDR(addr),`
`.DI(di[11:10]),`	`.DI(di[11:10]),`
`.EN(ce),`	`.EN(ce),`
`.WE(we),`	`.WE(we),`
`.DO(doq[11:10])`	`.DO(doq[11:10])`
Line 355...	Line 362...
`//`	`//`
`// Block 6`	`// Block 6`
`//`	`//`
`RAMB4_S2 ramb4_s2_6(`	`RAMB4_S2 ramb4_s2_6(`
`.CLK(clk),`	`.CLK(clk),`
`.RST(rst),`	`.RST(1'b0),`
`.ADDR(addr),`	`.ADDR(addr),`
`.DI(di[13:12]),`	`.DI(di[13:12]),`
`.EN(ce),`	`.EN(ce),`
`.WE(we),`	`.WE(we),`
`.DO(doq[13:12])`	`.DO(doq[13:12])`
Line 368...	Line 375...
`//`	`//`
`// Block 7`	`// Block 7`
`//`	`//`
`RAMB4_S2 ramb4_s2_7(`	`RAMB4_S2 ramb4_s2_7(`
`.CLK(clk),`	`.CLK(clk),`
`.RST(rst),`	`.RST(1'b0),`
`.ADDR(addr),`	`.ADDR(addr),`
`.DI(di[15:14]),`	`.DI(di[15:14]),`
`.EN(ce),`	`.EN(ce),`
`.WE(we),`	`.WE(we),`
`.DO(doq[15:14])`	`.DO(doq[15:14])`
Line 381...	Line 388...
`//`	`//`
`// Block 8`	`// Block 8`
`//`	`//`
`RAMB4_S2 ramb4_s2_8(`	`RAMB4_S2 ramb4_s2_8(`
`.CLK(clk),`	`.CLK(clk),`
`.RST(rst),`	`.RST(1'b0),`
`.ADDR(addr),`	`.ADDR(addr),`
`.DI(di[17:16]),`	`.DI(di[17:16]),`
`.EN(ce),`	`.EN(ce),`
`.WE(we),`	`.WE(we),`
`.DO(doq[17:16])`	`.DO(doq[17:16])`
Line 394...	Line 401...
`//`	`//`
`// Block 9`	`// Block 9`
`//`	`//`
`RAMB4_S2 ramb4_s2_9(`	`RAMB4_S2 ramb4_s2_9(`
`.CLK(clk),`	`.CLK(clk),`
`.RST(rst),`	`.RST(1'b0),`
`.ADDR(addr),`	`.ADDR(addr),`
`.DI(di[19:18]),`	`.DI(di[19:18]),`
`.EN(ce),`	`.EN(ce),`
`.WE(we),`	`.WE(we),`
`.DO(doq[19:18])`	`.DO(doq[19:18])`
Line 407...	Line 414...
`//`	`//`
`// Block 10`	`// Block 10`
`//`	`//`
`RAMB4_S2 ramb4_s2_10(`	`RAMB4_S2 ramb4_s2_10(`
`.CLK(clk),`	`.CLK(clk),`
`.RST(rst),`	`.RST(1'b0),`
`.ADDR(addr),`	`.ADDR(addr),`
`.DI(di[21:20]),`	`.DI(di[21:20]),`
`.EN(ce),`	`.EN(ce),`
`.WE(we),`	`.WE(we),`
`.DO(doq[21:20])`	`.DO(doq[21:20])`
Line 420...	Line 427...
`//`	`//`
`// Block 11`	`// Block 11`
`//`	`//`
`RAMB4_S2 ramb4_s2_11(`	`RAMB4_S2 ramb4_s2_11(`
`.CLK(clk),`	`.CLK(clk),`
`.RST(rst),`	`.RST(1'b0),`
`.ADDR(addr),`	`.ADDR(addr),`
`.DI(di[23:22]),`	`.DI(di[23:22]),`
`.EN(ce),`	`.EN(ce),`
`.WE(we),`	`.WE(we),`
`.DO(doq[23:22])`	`.DO(doq[23:22])`
Line 433...	Line 440...
`//`	`//`
`// Block 12`	`// Block 12`
`//`	`//`
`RAMB4_S2 ramb4_s2_12(`	`RAMB4_S2 ramb4_s2_12(`
`.CLK(clk),`	`.CLK(clk),`
`.RST(rst),`	`.RST(1'b0),`
`.ADDR(addr),`	`.ADDR(addr),`
`.DI(di[25:24]),`	`.DI(di[25:24]),`
`.EN(ce),`	`.EN(ce),`
`.WE(we),`	`.WE(we),`
`.DO(doq[25:24])`	`.DO(doq[25:24])`
Line 446...	Line 453...
`//`	`//`
`// Block 13`	`// Block 13`
`//`	`//`
`RAMB4_S2 ramb4_s2_13(`	`RAMB4_S2 ramb4_s2_13(`
`.CLK(clk),`	`.CLK(clk),`
`.RST(rst),`	`.RST(1'b0),`
`.ADDR(addr),`	`.ADDR(addr),`
`.DI(di[27:26]),`	`.DI(di[27:26]),`
`.EN(ce),`	`.EN(ce),`
`.WE(we),`	`.WE(we),`
`.DO(doq[27:26])`	`.DO(doq[27:26])`
Line 459...	Line 466...
`//`	`//`
`// Block 14`	`// Block 14`
`//`	`//`
`RAMB4_S2 ramb4_s2_14(`	`RAMB4_S2 ramb4_s2_14(`
`.CLK(clk),`	`.CLK(clk),`
`.RST(rst),`	`.RST(1'b0),`
`.ADDR(addr),`	`.ADDR(addr),`
`.DI(di[29:28]),`	`.DI(di[29:28]),`
`.EN(ce),`	`.EN(ce),`
`.WE(we),`	`.WE(we),`
`.DO(doq[29:28])`	`.DO(doq[29:28])`
Line 472...	Line 479...
`//`	`//`
`// Block 15`	`// Block 15`
`//`	`//`
`RAMB4_S2 ramb4_s2_15(`	`RAMB4_S2 ramb4_s2_15(`
`.CLK(clk),`	`.CLK(clk),`
`.RST(rst),`	`.RST(1'b0),`
`.ADDR(addr),`	`.ADDR(addr),`
`.DI(di[31:30]),`	`.DI(di[31:30]),`
`.EN(ce),`	`.EN(ce),`
`.WE(we),`	`.WE(we),`
`.DO(doq[31:30])`	`.DO(doq[31:30])`
Line 497...	Line 504...
`//`	`//`
`// Block 0`	`// Block 0`
`//`	`//`
`RAMB16_S9 ramb16_s9_0(`	`RAMB16_S9 ramb16_s9_0(`
`.CLK(clk),`	`.CLK(clk),`
`.SSR(rst),`	`.SSR(1'b0),`
`.ADDR(addr),`	`.ADDR(addr),`
`.DI(di[7:0]),`	`.DI(di[7:0]),`
`.DIP(1'b0),`	`.DIP(1'b0),`
`.EN(ce),`	`.EN(ce),`
`.WE(we),`	`.WE(we),`
Line 512...	Line 519...
`//`	`//`
`// Block 1`	`// Block 1`
`//`	`//`
`RAMB16_S9 ramb16_s9_1(`	`RAMB16_S9 ramb16_s9_1(`
`.CLK(clk),`	`.CLK(clk),`
`.SSR(rst),`	`.SSR(1'b0),`
`.ADDR(addr),`	`.ADDR(addr),`
`.DI(di[15:8]),`	`.DI(di[15:8]),`
`.DIP(1'b0),`	`.DIP(1'b0),`
`.EN(ce),`	`.EN(ce),`
`.WE(we),`	`.WE(we),`
Line 527...	Line 534...
`//`	`//`
`// Block 2`	`// Block 2`
`//`	`//`
`RAMB16_S9 ramb16_s9_2(`	`RAMB16_S9 ramb16_s9_2(`
`.CLK(clk),`	`.CLK(clk),`
`.SSR(rst),`	`.SSR(1'b0),`
`.ADDR(addr),`	`.ADDR(addr),`
`.DI(di[23:16]),`	`.DI(di[23:16]),`
`.DIP(1'b0),`	`.DIP(1'b0),`
`.EN(ce),`	`.EN(ce),`
`.WE(we),`	`.WE(we),`
Line 542...	Line 549...
`//`	`//`
`// Block 3`	`// Block 3`
`//`	`//`
`RAMB16_S9 ramb16_s9_3(`	`RAMB16_S9 ramb16_s9_3(`
`.CLK(clk),`	`.CLK(clk),`
`.SSR(rst),`	`.SSR(1'b0),`
`.ADDR(addr),`	`.ADDR(addr),`
`.DI(di[31:24]),`	`.DI(di[31:24]),`
`.DIP(1'b0),`	`.DIP(1'b0),`
`.EN(ce),`	`.EN(ce),`
`.WE(we),`	`.WE(we),`

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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_2048x32.v] - Diff between revs 10 and 142