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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_2048x8.v] - Diff between revs 10 and 142

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Rev 10 Rev 142
Line 61... Line 61...
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: or1200_spram_2048x8.v,v $
 
// Revision 2.0  2010/06/30 11:00:00  ORSoC
 
// Minor update: 
 
// Coding style changed.
 
//
 
// Revision 1.9  2005/10/19 11:37:56  jcastillo
 
// Added support for RAMB16 Xilinx4/Spartan3 primitives
 
//
// Revision 1.8  2004/06/08 18:15:32  lampret
// Revision 1.8  2004/06/08 18:15:32  lampret
// Changed behavior of the simulation generic models
// Changed behavior of the simulation generic models
//
//
// Revision 1.7  2004/04/05 08:29:57  lampret
// Revision 1.7  2004/04/05 08:29:57  lampret
// Merged branch_qmem into main tree.
// Merged branch_qmem into main tree.
Line 274... Line 281...
//
//
// Block 0
// Block 0
//
//
RAMB4_S2 ramb4_s2_0(
RAMB4_S2 ramb4_s2_0(
        .CLK(clk),
        .CLK(clk),
        .RST(rst),
        .RST(1'b0),
        .ADDR(addr),
        .ADDR(addr),
        .DI(di[1:0]),
        .DI(di[1:0]),
        .EN(ce),
        .EN(ce),
        .WE(we),
        .WE(we),
        .DO(doq[1:0])
        .DO(doq[1:0])
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//
//
// Block 1
// Block 1
//
//
RAMB4_S2 ramb4_s2_1(
RAMB4_S2 ramb4_s2_1(
        .CLK(clk),
        .CLK(clk),
        .RST(rst),
        .RST(1'b0),
        .ADDR(addr),
        .ADDR(addr),
        .DI(di[3:2]),
        .DI(di[3:2]),
        .EN(ce),
        .EN(ce),
        .WE(we),
        .WE(we),
        .DO(doq[3:2])
        .DO(doq[3:2])
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//
//
// Block 2
// Block 2
//
//
RAMB4_S2 ramb4_s2_2(
RAMB4_S2 ramb4_s2_2(
        .CLK(clk),
        .CLK(clk),
        .RST(rst),
        .RST(1'b0),
        .ADDR(addr),
        .ADDR(addr),
        .DI(di[5:4]),
        .DI(di[5:4]),
        .EN(ce),
        .EN(ce),
        .WE(we),
        .WE(we),
        .DO(doq[5:4])
        .DO(doq[5:4])
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//
//
// Block 3
// Block 3
//
//
RAMB4_S2 ramb4_s2_3(
RAMB4_S2 ramb4_s2_3(
        .CLK(clk),
        .CLK(clk),
        .RST(rst),
        .RST(1'b0),
        .ADDR(addr),
        .ADDR(addr),
        .DI(di[7:6]),
        .DI(di[7:6]),
        .EN(ce),
        .EN(ce),
        .WE(we),
        .WE(we),
        .DO(doq[7:6])
        .DO(doq[7:6])
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// Added By Nir Mor
// Added By Nir Mor
//
//
 
 
RAMB16_S9 ramb16_s9(
RAMB16_S9 ramb16_s9(
        .CLK(clk),
        .CLK(clk),
        .SSR(rst),
        .SSR(1'b0),
        .ADDR(addr),
        .ADDR(addr),
        .DI(di),
        .DI(di),
        .DIP(1'b0),
        .DIP(1'b0),
        .EN(ce),
        .EN(ce),
        .WE(we),
        .WE(we),

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