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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_32_bw.v] - Diff between revs 142 and 258
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| Rev 142 |
Rev 258 |
| Line 102... |
Line 102... |
//
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//
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//
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//
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// Generic RAM's registers and wires
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// Generic RAM's registers and wires
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//
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//
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`ifdef OR1200_ACTEL
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`ifdef OR1200_GENERIC
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reg [7:0] mem0 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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reg [7:0] mem0 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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reg [7:0] mem1 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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reg [7:0] mem1 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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reg [7:0] mem2 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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reg [7:0] mem2 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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reg [7:0] mem3 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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reg [7:0] mem3 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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`else
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`else
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| Line 125... |
Line 125... |
//
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//
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// RAM read address register
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// RAM read address register
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//
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//
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always @(posedge clk)
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always @(posedge clk)
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if (ce)
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if (ce)
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addr_reg <= #1 addr;
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addr_reg <= addr;
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//
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//
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// RAM write
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// RAM write - big endian selection
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//
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//
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always @(posedge clk)
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always @(posedge clk)
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if (ce) begin
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if (ce) begin
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if (we[0])
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mem0[addr] <= #1 di[31:24];
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if (we[1])
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mem1[addr] <= #1 di[23:16];
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if (we[2])
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mem2[addr] <= #1 di[15:08];
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if (we[3])
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if (we[3])
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mem3[addr] <= #1 di[07:00];
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mem0[addr] <= di[31:24];
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if (we[2])
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mem1[addr] <= di[23:16];
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if (we[1])
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mem2[addr] <= di[15:08];
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if (we[0])
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mem3[addr] <= di[07:00];
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end
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end
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endmodule // or1200_spram
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endmodule // or1200_spram
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