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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_32_bw.v] - Diff between revs 142 and 258

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Rev 142 Rev 258
Line 102... Line 102...
   //
   //
 
 
   //
   //
   // Generic RAM's registers and wires
   // Generic RAM's registers and wires
   //
   //
`ifdef OR1200_ACTEL
`ifdef OR1200_GENERIC
   reg [7:0]                               mem0 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
   reg [7:0]                               mem0 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
   reg [7:0]                               mem1 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
   reg [7:0]                               mem1 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
   reg [7:0]                               mem2 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
   reg [7:0]                               mem2 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
   reg [7:0]                               mem3 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
   reg [7:0]                               mem3 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
`else
`else
Line 125... Line 125...
   //
   //
   // RAM read address register
   // RAM read address register
   //
   //
   always @(posedge clk)
   always @(posedge clk)
     if (ce)
     if (ce)
       addr_reg <= #1 addr;
       addr_reg <=  addr;
 
 
   //
   //
   // RAM write
   // RAM write - big endian selection
   //
   //
   always @(posedge clk)
   always @(posedge clk)
     if (ce) begin
     if (ce) begin
       if (we[0])
 
         mem0[addr] <= #1 di[31:24];
 
       if (we[1])
 
         mem1[addr] <= #1 di[23:16];
 
       if (we[2])
 
         mem2[addr] <= #1 di[15:08];
 
       if (we[3])
       if (we[3])
         mem3[addr] <= #1 di[07:00];
         mem0[addr] <=  di[31:24];
 
       if (we[2])
 
         mem1[addr] <=  di[23:16];
 
       if (we[1])
 
         mem2[addr] <=  di[15:08];
 
       if (we[0])
 
         mem3[addr] <=  di[07:00];
     end
     end
 
 
endmodule // or1200_spram
endmodule // or1200_spram
 
 
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