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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_32x24.v] - Diff between revs 10 and 142

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Rev 10 Rev 142
Line 61... Line 61...
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: or1200_spram_32x24.v,v $
 
// Revision 2.0  2010/06/30 11:00:00  ORSoC
 
// Minor update: 
 
// Coding style changed.
 
//
 
// Revision 1.3  2005/10/19 11:37:56  jcastillo
 
// Added support for RAMB16 Xilinx4/Spartan3 primitives
 
//
// Revision 1.2  2004/06/08 18:15:32  lampret
// Revision 1.2  2004/06/08 18:15:32  lampret
// Changed behavior of the simulation generic models
// Changed behavior of the simulation generic models
//
//
// Revision 1.1  2004/04/08 11:00:46  simont
// Revision 1.1  2004/04/08 11:00:46  simont
// Add support for 512B instruction cache.
// Add support for 512B instruction cache.
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//
//
// Block 0
// Block 0
//
//
RAMB4_S16 ramb4_s16_0(
RAMB4_S16 ramb4_s16_0(
        .CLK(clk),
        .CLK(clk),
        .RST(rst),
        .RST(1'b0),
        .ADDR({3'h0, addr}),
        .ADDR({3'h0, addr}),
        .DI(di[15:0]),
        .DI(di[15:0]),
        .EN(ce),
        .EN(ce),
        .WE(we),
        .WE(we),
        .DO(doq[15:0])
        .DO(doq[15:0])
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//
//
// Block 1
// Block 1
//
//
RAMB4_S16 ramb4_s16_1(
RAMB4_S16 ramb4_s16_1(
        .CLK(clk),
        .CLK(clk),
        .RST(rst),
        .RST(1'b0),
        .ADDR({3'h0, addr}),
        .ADDR({3'h0, addr}),
        .DI({8'h00, di[23:16]}),
        .DI({8'h00, di[23:16]}),
        .EN(ce),
        .EN(ce),
        .WE(we),
        .WE(we),
        .DO({unconnected, doq[23:16]})
        .DO({unconnected, doq[23:16]})
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// Added By Nir Mor
// Added By Nir Mor
//
//
 
 
RAMB16_S36 ramb16_s36(
RAMB16_S36 ramb16_s36(
        .CLK(clk),
        .CLK(clk),
        .SSR(rst),
        .SSR(1'b0),
        .ADDR({4'b0000, addr}),
        .ADDR({4'b0000, addr}),
        .DI({8'h00, di}),
        .DI({8'h00, di}),
        .DIP(4'h0),
        .DIP(4'h0),
        .EN(ce),
        .EN(ce),
        .WE(we),
        .WE(we),

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