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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_64x14.v] - Diff between revs 10 and 142

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Rev 10	Rev 142
Line 61...	Line 61...
`//// ////`	`//// ////`
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: or1200_spram_64x14.v,v $`
	`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
	`// Minor update:`
	`// Coding style changed.`
	`//`
	`// Revision 1.9 2005/10/19 11:37:56 jcastillo`
	`// Added support for RAMB16 Xilinx4/Spartan3 primitives`
	`//`
`// Revision 1.8 2004/06/08 18:15:32 lampret`	`// Revision 1.8 2004/06/08 18:15:32 lampret`
`// Changed behavior of the simulation generic models`	`// Changed behavior of the simulation generic models`
`//`	`//`
`// Revision 1.7 2004/04/05 08:29:57 lampret`	`// Revision 1.7 2004/04/05 08:29:57 lampret`
`// Merged branch_qmem into main tree.`	`// Merged branch_qmem into main tree.`
Line 282...	Line 289...
`//`	`//`
`// Block 0`	`// Block 0`
`//`	`//`
`RAMB4_S16 ramb4_s16_0(`	`RAMB4_S16 ramb4_s16_0(`
`.CLK(clk),`	`.CLK(clk),`
`.RST(rst),`	`.RST(1'b0),`
`.ADDR({2'b00, addr}),`	`.ADDR({2'b00, addr}),`
`.DI({2'b00, di[13:0]}),`	`.DI({2'b00, di[13:0]}),`
`.EN(ce),`	`.EN(ce),`
`.WE(we),`	`.WE(we),`
`.DO({unconnected, doq[13:0]})`	`.DO({unconnected, doq[13:0]})`
Line 302...	Line 309...
`// Virtex4/Spartan3E`	`// Virtex4/Spartan3E`
`//`	`//`

`RAMB16_S18 ramb16_s18(`	`RAMB16_S18 ramb16_s18(`
`.CLK(clk),`	`.CLK(clk),`
`.SSR(rst),`	`.SSR(1'b0),`
`.ADDR({4'b0000, addr}),`	`.ADDR({4'b0000, addr}),`
`.DI({2'b00, di[13:0]}),`	`.DI({2'b00, di[13:0]}),`
`.DIP(2'b00),`	`.DIP(2'b00),`
`.EN(ce),`	`.EN(ce),`
`.WE(we),`	`.WE(we),`

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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_64x14.v] - Diff between revs 10 and 142