OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_64x14.v] - Diff between revs 142 and 258

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 142 Rev 258
Line 376... Line 376...
//
//
// RAM address register
// RAM address register
//
//
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                addr_reg <= #1 {aw{1'b0}};
                addr_reg <=  {aw{1'b0}};
        else if (ce)
        else if (ce)
                addr_reg <= #1 addr;
                addr_reg <=  addr;
 
 
//
//
// RAM write
// RAM write
//
//
always @(posedge clk)
always @(posedge clk)
        if (ce && we)
        if (ce && we)
                mem[addr] <= #1 di;
                mem[addr] <=  di;
 
 
`endif  // !OR1200_ALTERA_LPM
`endif  // !OR1200_ALTERA_LPM
`endif  // !OR1200_XILINX_RAMB16
`endif  // !OR1200_XILINX_RAMB16
`endif  // !OR1200_XILINX_RAMB4
`endif  // !OR1200_XILINX_RAMB4
`endif  // !OR1200_VIRTUALSILICON_SSP
`endif  // !OR1200_VIRTUALSILICON_SSP

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.