URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_64x24.v] - Diff between revs 10 and 142

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Rev 10	Rev 142
Line 61...	Line 61...
`//// ////`	`//// ////`
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: or1200_spram_64x24.v,v $`
	`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
	`// Minor update:`
	`// Coding style changed.`
	`//`
	`// Revision 1.9 2005/10/19 11:37:56 jcastillo`
	`// Added support for RAMB16 Xilinx4/Spartan3 primitives`
	`//`
`// Revision 1.8 2004/06/08 18:15:32 lampret`	`// Revision 1.8 2004/06/08 18:15:32 lampret`
`// Changed behavior of the simulation generic models`	`// Changed behavior of the simulation generic models`
`//`	`//`
`// Revision 1.7 2004/04/05 08:29:57 lampret`	`// Revision 1.7 2004/04/05 08:29:57 lampret`
`// Merged branch_qmem into main tree.`	`// Merged branch_qmem into main tree.`
Line 284...	Line 291...
`//`	`//`
`// Block 0`	`// Block 0`
`//`	`//`
`RAMB4_S16 ramb4_s16_0(`	`RAMB4_S16 ramb4_s16_0(`
`.CLK(clk),`	`.CLK(clk),`
`.RST(rst),`	`.RST(1'b0),`
`.ADDR({2'b00, addr}),`	`.ADDR({2'b00, addr}),`
`.DI(di[15:0]),`	`.DI(di[15:0]),`
`.EN(ce),`	`.EN(ce),`
`.WE(we),`	`.WE(we),`
`.DO(doq[15:0])`	`.DO(doq[15:0])`
Line 297...	Line 304...
`//`	`//`
`// Block 1`	`// Block 1`
`//`	`//`
`RAMB4_S16 ramb4_s16_1(`	`RAMB4_S16 ramb4_s16_1(`
`.CLK(clk),`	`.CLK(clk),`
`.RST(rst),`	`.RST(1'b0),`
`.ADDR({2'b00, addr}),`	`.ADDR({2'b00, addr}),`
`.DI({8'h00, di[23:16]}),`	`.DI({8'h00, di[23:16]}),`
`.EN(ce),`	`.EN(ce),`
`.WE(we),`	`.WE(we),`
`.DO({unconnected, doq[23:16]})`	`.DO({unconnected, doq[23:16]})`
Line 319...	Line 326...
`// Added By Nir Mor`	`// Added By Nir Mor`
`//`	`//`

`RAMB16_S36 ramb16_s36(`	`RAMB16_S36 ramb16_s36(`
`.CLK(clk),`	`.CLK(clk),`
`.SSR(rst),`	`.SSR(1'b0),`
`.ADDR({3'b000, addr}),`	`.ADDR({3'b000, addr}),`
`.DI({8'h00,di}),`	`.DI({8'h00,di}),`
`.DIP(4'h0),`	`.DIP(4'h0),`
`.EN(ce),`	`.EN(ce),`
`.WE(we),`	`.WE(we),`

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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_64x24.v] - Diff between revs 10 and 142