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| Rev 353 |
Rev 358 |
| Line 325... |
Line 325... |
assign carry = sr[`OR1200_SR_CY];
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assign carry = sr[`OR1200_SR_CY];
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//
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//
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// Supervision register
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// Supervision register
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or `OR1200_RST_EVENT rst)
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if (rst)
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if (rst == `OR1200_RST_VALUE)
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sr_reg <= {2'h1, `OR1200_SR_EPH_DEF, {`OR1200_SR_WIDTH-4{1'b0}}, 1'b1};
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sr_reg <= {2'h1, `OR1200_SR_EPH_DEF, {`OR1200_SR_WIDTH-4{1'b0}}, 1'b1};
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else if (except_started)
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else if (except_started)
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sr_reg <= to_sr[`OR1200_SR_WIDTH-1:0];
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sr_reg <= to_sr[`OR1200_SR_WIDTH-1:0];
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else if (sr_we)
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else if (sr_we)
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sr_reg <= to_sr[`OR1200_SR_WIDTH-1:0];
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sr_reg <= to_sr[`OR1200_SR_WIDTH-1:0];
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// EPH part of Supervision register
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// EPH part of Supervision register
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always @(posedge clk or posedge rst)
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always @(posedge clk or `OR1200_RST_EVENT rst)
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// default value
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// default value
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if (rst) begin
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if (rst == `OR1200_RST_VALUE) begin
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sr_reg_bit_eph <= `OR1200_SR_EPH_DEF;
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sr_reg_bit_eph <= `OR1200_SR_EPH_DEF;
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sr_reg_bit_eph_select <= 1'b1; // select async. value due to reset state
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sr_reg_bit_eph_select <= 1'b1; // select async. value due to reset state
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end
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end
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// selected value (different from default) is written into FF after reset state
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// selected value (different from default) is written into FF after reset state
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else if (sr_reg_bit_eph_select) begin
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else if (sr_reg_bit_eph_select) begin
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