URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
Rev 358 |
Rev 364 |
Line 363... |
Line 363... |
// simulator, since functions with no inputs are not allowed in IEEE
|
// simulator, since functions with no inputs are not allowed in IEEE
|
// 1364-2001.
|
// 1364-2001.
|
|
|
function [31:0] get_sr;
|
function [31:0] get_sr;
|
// verilator public
|
// verilator public
|
get_sr = sr;
|
get_sr = {{32-`OR1200_SR_WIDTH{1'b0}},sr};
|
endfunction // get_sr
|
endfunction // get_sr
|
|
|
function [31:0] get_epcr;
|
function [31:0] get_epcr;
|
// verilator public
|
// verilator public
|
get_epcr = epcr;
|
get_epcr = epcr;
|
Line 378... |
Line 378... |
get_eear = eear;
|
get_eear = eear;
|
endfunction // get_eear
|
endfunction // get_eear
|
|
|
function [31:0] get_esr;
|
function [31:0] get_esr;
|
// verilator public
|
// verilator public
|
get_esr = esr;
|
get_esr = {{32-`OR1200_SR_WIDTH{1'b0}},esr};
|
endfunction // get_esr
|
endfunction // get_esr
|
|
|
`endif
|
`endif
|
|
|
|
|
Line 390... |
Line 390... |
// MTSPR/MFSPR interface
|
// MTSPR/MFSPR interface
|
//
|
//
|
always @(spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or
|
always @(spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or
|
spr_dat_fpu or
|
spr_dat_fpu or
|
spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin
|
spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin
|
casex (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
|
casez (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
|
`OR1200_SPR_GROUP_SYS:
|
`OR1200_SPR_GROUP_SYS:
|
to_wbmux = sys_data;
|
to_wbmux = sys_data;
|
`OR1200_SPR_GROUP_TT:
|
`OR1200_SPR_GROUP_TT:
|
to_wbmux = spr_dat_tt;
|
to_wbmux = spr_dat_tt;
|
`OR1200_SPR_GROUP_PIC:
|
`OR1200_SPR_GROUP_PIC:
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.