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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_sprs.v] - Diff between revs 187 and 258

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Rev 187 Rev 258
Line 61... Line 61...
                epcr, eear, esr, except_started,
                epcr, eear, esr, except_started,
                to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr_we, to_sr, sr,
                to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr_we, to_sr, sr,
                spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc, spr_dat_mac,
                spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc, spr_dat_mac,
                boot_adr_sel_i,
                boot_adr_sel_i,
 
 
                // Floating point control register and SPR input
                // Floating point SPR input
                fpcsr, fpcsr_we, spr_dat_fpu,
                fpcsr, fpcsr_we, spr_dat_fpu,
 
 
                // From/to other RISC units
                // From/to other RISC units
                spr_dat_pic, spr_dat_tt, spr_dat_pm,
                spr_dat_pic, spr_dat_tt, spr_dat_pm,
                spr_dat_dmmu, spr_dat_immu, spr_dat_du,
                spr_dat_dmmu, spr_dat_immu, spr_dat_du,
Line 286... Line 286...
assign ppc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_PPC));
assign ppc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_PPC));
assign sr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_SR));
assign sr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_SR));
assign epcr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EPCR));
assign epcr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EPCR));
assign eear_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EEAR));
assign eear_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EEAR));
assign esr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_ESR));
assign esr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_ESR));
`ifdef OR1200_FPU_IMPLEMENTED
 
assign fpcsr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_FPCSR));
assign fpcsr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_FPCSR));
`else
 
assign fpcsr_sel = 0;
 
`endif
 
 
 
 
 
//
//
// Write enables for system SPRs
// Write enables for system SPRs
//
//
assign sr_we = (spr_we && sr_sel) | (branch_op == `OR1200_BRANCHOP_RFE) | flag_we | cy_we;
assign sr_we = (spr_we && sr_sel) | (branch_op == `OR1200_BRANCHOP_RFE) | flag_we | cy_we;
assign pc_we = (du_write && (npc_sel | ppc_sel));
assign pc_we = (du_write && (npc_sel | ppc_sel));
assign epcr_we = (spr_we && epcr_sel);
assign epcr_we = (spr_we && epcr_sel);
assign eear_we = (spr_we && eear_sel);
assign eear_we = (spr_we && eear_sel);
assign esr_we = (spr_we && esr_sel);
assign esr_we = (spr_we && esr_sel);
`ifdef OR1200_FPU_IMPLEMENTED
 
assign fpcsr_we = (spr_we && fpcsr_sel);
assign fpcsr_we = (spr_we && fpcsr_sel);
`else
 
assign fpcsr_we = 0;
 
`endif
 
 
 
//
//
// Output from system SPRs
// Output from system SPRs
//
//
assign sys_data = (spr_dat_cfgr & {32{cfgr_sel}}) |
assign sys_data = (spr_dat_cfgr & {32{cfgr_sel}}) |
Line 317... Line 309...
                  (spr_dat_npc & {32{npc_sel}}) |
                  (spr_dat_npc & {32{npc_sel}}) |
                  (spr_dat_ppc & {32{ppc_sel}}) |
                  (spr_dat_ppc & {32{ppc_sel}}) |
                  ({{32-`OR1200_SR_WIDTH{1'b0}},sr} & {32{sr_sel}}) |
                  ({{32-`OR1200_SR_WIDTH{1'b0}},sr} & {32{sr_sel}}) |
                  (epcr & {32{epcr_sel}}) |
                  (epcr & {32{epcr_sel}}) |
                  (eear & {32{eear_sel}}) |
                  (eear & {32{eear_sel}}) |
`ifdef OR1200_FPU_IMPLEMENTED
 
                  ({{32-`OR1200_FPCSR_WIDTH{1'b0}},fpcsr} & {32{fpcsr_sel}}) |
                  ({{32-`OR1200_FPCSR_WIDTH{1'b0}},fpcsr} & {32{fpcsr_sel}}) |
`endif
 
                  ({{32-`OR1200_SR_WIDTH{1'b0}},esr} & {32{esr_sel}});
                  ({{32-`OR1200_SR_WIDTH{1'b0}},esr} & {32{esr_sel}});
 
 
//
//
// Flag alias
// Flag alias
//
//
Line 337... Line 327...
//
//
// Supervision register
// Supervision register
//
//
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        if (rst)
        if (rst)
                sr_reg <= #1 {2'h1, `OR1200_SR_EPH_DEF, {`OR1200_SR_WIDTH-4{1'b0}}, 1'b1};
                sr_reg <=  {2'h1, `OR1200_SR_EPH_DEF, {`OR1200_SR_WIDTH-4{1'b0}}, 1'b1};
        else if (except_started)
        else if (except_started)
                sr_reg <= #1 to_sr[`OR1200_SR_WIDTH-1:0];
                sr_reg <=  to_sr[`OR1200_SR_WIDTH-1:0];
        else if (sr_we)
        else if (sr_we)
                sr_reg <= #1 to_sr[`OR1200_SR_WIDTH-1:0];
                sr_reg <=  to_sr[`OR1200_SR_WIDTH-1:0];
 
 
// EPH part of Supervision register
// EPH part of Supervision register
always @(posedge clk or posedge rst)
always @(posedge clk or posedge rst)
        // default value 
        // default value 
        if (rst) begin
        if (rst) begin
                sr_reg_bit_eph <= #1 `OR1200_SR_EPH_DEF;
                sr_reg_bit_eph <=  `OR1200_SR_EPH_DEF;
                sr_reg_bit_eph_select <= #1 1'b1;       // select async. value due to reset state
                sr_reg_bit_eph_select <=  1'b1; // select async. value due to reset state
        end
        end
        // selected value (different from default) is written into FF after reset state
        // selected value (different from default) is written into FF after reset state
        else if (sr_reg_bit_eph_select) begin
        else if (sr_reg_bit_eph_select) begin
                sr_reg_bit_eph <= #1 boot_adr_sel_i;    // dynamic value can only be assigned to FF out of reset! 
                sr_reg_bit_eph <=  boot_adr_sel_i;      // dynamic value can only be assigned to FF out of reset! 
                sr_reg_bit_eph_select <= #1 1'b0;       // select FF value 
                sr_reg_bit_eph_select <=  1'b0; // select FF value 
        end
        end
        else if (sr_we) begin
        else if (sr_we) begin
                sr_reg_bit_eph <= #1 to_sr[`OR1200_SR_EPH];
                sr_reg_bit_eph <=  to_sr[`OR1200_SR_EPH];
        end
        end
 
 
// select async. value of EPH bit after reset 
// select async. value of EPH bit after reset 
assign  sr_reg_bit_eph_muxed = (sr_reg_bit_eph_select) ? boot_adr_sel_i : sr_reg_bit_eph;
assign  sr_reg_bit_eph_muxed = (sr_reg_bit_eph_select) ? boot_adr_sel_i : sr_reg_bit_eph;
 
 
Line 370... Line 360...
 
 
//
//
// MTSPR/MFSPR interface
// MTSPR/MFSPR interface
//
//
always @(spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or
always @(spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or
`ifdef OR1200_FPU_IMPLEMENTED
 
         spr_dat_fpu or
         spr_dat_fpu or
`endif
 
        spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin
        spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin
                casex (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
                casex (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
                        `OR1200_SPR_GROUP_SYS:
                        `OR1200_SPR_GROUP_SYS:
                                to_wbmux = sys_data;
                                to_wbmux = sys_data;
                        `OR1200_SPR_GROUP_TT:
                        `OR1200_SPR_GROUP_TT:
Line 389... Line 377...
                                to_wbmux = spr_dat_dmmu;
                                to_wbmux = spr_dat_dmmu;
                        `OR1200_SPR_GROUP_IMMU:
                        `OR1200_SPR_GROUP_IMMU:
                                to_wbmux = spr_dat_immu;
                                to_wbmux = spr_dat_immu;
                        `OR1200_SPR_GROUP_MAC:
                        `OR1200_SPR_GROUP_MAC:
                                to_wbmux = spr_dat_mac;
                                to_wbmux = spr_dat_mac;
`ifdef OR1200_FPU_IMPLEMENTED
 
                        `OR1200_SPR_GROUP_FPU:
                        `OR1200_SPR_GROUP_FPU:
                                 to_wbmux = spr_dat_fpu;
                                 to_wbmux = spr_dat_fpu;
`endif
 
                        default: //`OR1200_SPR_GROUP_DU:
                        default: //`OR1200_SPR_GROUP_DU:
                                to_wbmux = spr_dat_du;
                                to_wbmux = spr_dat_du;
                endcase
                endcase
end
end
 
 

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