| Line 41... |
Line 41... |
//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: or1200_sprs.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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|
// Major update:
|
|
// Structure reordered and bugs fixed.
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//
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// Revision 1.11 2004/04/05 08:29:57 lampret
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// Merged branch_qmem into main tree.
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//
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// Revision 1.9.4.1 2003/12/17 13:43:38 simons
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// Revision 1.9.4.1 2003/12/17 13:43:38 simons
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// Exception prefix configuration changed.
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// Exception prefix configuration changed.
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//
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//
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// Revision 1.9 2002/09/07 05:42:02 lampret
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// Revision 1.9 2002/09/07 05:42:02 lampret
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// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
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// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
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| Line 112... |
Line 119... |
// Clk & Rst
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// Clk & Rst
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clk, rst,
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clk, rst,
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|
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// Internal CPU interface
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// Internal CPU interface
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flagforw, flag_we, flag, cyforw, cy_we, carry,
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flagforw, flag_we, flag, cyforw, cy_we, carry,
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addrbase, addrofs, dat_i, alu_op, branch_op,
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addrbase, addrofs, dat_i, branch_op, ex_spr_read, ex_spr_write,
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epcr, eear, esr, except_started,
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epcr, eear, esr, except_started,
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to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr_we, to_sr, sr,
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to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr_we, to_sr, sr,
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spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc, spr_dat_mac,
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spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc, spr_dat_mac,
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boot_adr_sel_i,
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|
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// From/to other RISC units
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// From/to other RISC units
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spr_dat_pic, spr_dat_tt, spr_dat_pm,
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spr_dat_pic, spr_dat_tt, spr_dat_pm,
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spr_dat_dmmu, spr_dat_immu, spr_dat_du,
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spr_dat_dmmu, spr_dat_immu, spr_dat_du,
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spr_addr, spr_dat_o, spr_cs, spr_we,
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spr_addr, spr_dat_o, spr_cs, spr_we,
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| Line 147... |
Line 155... |
input cy_we; // From ALU
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input cy_we; // From ALU
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output carry; // SR[CY]
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output carry; // SR[CY]
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input [width-1:0] addrbase; // SPR base address
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input [width-1:0] addrbase; // SPR base address
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input [15:0] addrofs; // SPR offset
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input [15:0] addrofs; // SPR offset
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input [width-1:0] dat_i; // SPR write data
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input [width-1:0] dat_i; // SPR write data
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input [`OR1200_ALUOP_WIDTH-1:0] alu_op; // ALU operation
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input ex_spr_read; // l.mfspr in EX
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input ex_spr_write; // l.mtspr in EX
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input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch operation
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input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch operation
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input [width-1:0] epcr; // EPCR0
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input [width-1:0] epcr; // EPCR0
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input [width-1:0] eear; // EEAR0
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input [width-1:0] eear; // EEAR0
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input [`OR1200_SR_WIDTH-1:0] esr; // ESR0
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input [`OR1200_SR_WIDTH-1:0] esr; // ESR0
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input except_started; // Exception was started
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input except_started; // Exception was started
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| Line 166... |
Line 175... |
input [31:0] spr_dat_cfgr; // Data from CFGR
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input [31:0] spr_dat_cfgr; // Data from CFGR
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input [31:0] spr_dat_rf; // Data from RF
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input [31:0] spr_dat_rf; // Data from RF
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input [31:0] spr_dat_npc; // Data from NPC
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input [31:0] spr_dat_npc; // Data from NPC
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input [31:0] spr_dat_ppc; // Data from PPC
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input [31:0] spr_dat_ppc; // Data from PPC
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input [31:0] spr_dat_mac; // Data from MAC
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input [31:0] spr_dat_mac; // Data from MAC
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input boot_adr_sel_i;
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//
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//
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// To/from other RISC units
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// To/from other RISC units
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//
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//
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input [31:0] spr_dat_pic; // Data from PIC
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input [31:0] spr_dat_pic; // Data from PIC
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| Line 193... |
Line 203... |
output [width-1:0] du_dat_cpu; // Data from SPRS to DU
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output [width-1:0] du_dat_cpu; // Data from SPRS to DU
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//
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//
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// Internal regs & wires
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// Internal regs & wires
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//
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//
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reg [`OR1200_SR_WIDTH-1:0] sr_reg; // SR
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reg sr_reg_bit_eph; // SR_EPH bit
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reg sr_reg_bit_eph_select; // SR_EPH select
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wire sr_reg_bit_eph_muxed; // SR_EPH muxed bit
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reg [`OR1200_SR_WIDTH-1:0] sr; // SR
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reg [`OR1200_SR_WIDTH-1:0] sr; // SR
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reg write_spr; // Write SPR
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reg read_spr; // Read SPR
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reg [width-1:0] to_wbmux; // For l.mfspr
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reg [width-1:0] to_wbmux; // For l.mfspr
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wire cfgr_sel; // Select for cfg regs
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wire cfgr_sel; // Select for cfg regs
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wire rf_sel; // Select for RF
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wire rf_sel; // Select for RF
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wire npc_sel; // Select for NPC
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wire npc_sel; // Select for NPC
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wire ppc_sel; // Select for PPC
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wire ppc_sel; // Select for PPC
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| Line 207... |
Line 219... |
wire epcr_sel; // Select for EPCR0
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wire epcr_sel; // Select for EPCR0
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wire eear_sel; // Select for EEAR0
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wire eear_sel; // Select for EEAR0
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wire esr_sel; // Select for ESR0
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wire esr_sel; // Select for ESR0
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wire [31:0] sys_data; // Read data from system SPRs
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wire [31:0] sys_data; // Read data from system SPRs
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wire du_access; // Debug unit access
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wire du_access; // Debug unit access
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wire [`OR1200_ALUOP_WIDTH-1:0] sprs_op; // ALU operation
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reg [31:0] unqualified_cs; // Unqualified chip selects
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reg [31:0] unqualified_cs; // Unqualified chip selects
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wire ex_spr_write; // jb
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//
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//
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// Decide if it is debug unit access
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// Decide if it is debug unit access
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//
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//
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assign du_access = du_read | du_write;
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assign du_access = du_read | du_write;
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//
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//
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// Generate sprs opcode
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//
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assign sprs_op = du_write ? `OR1200_ALUOP_MTSR : du_read ? `OR1200_ALUOP_MFSR : alu_op;
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//
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// Generate SPR address from base address and offset
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// Generate SPR address from base address and offset
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// OR from debug unit address
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// OR from debug unit address
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//
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//
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assign spr_addr = du_access ? du_addr : addrbase | {16'h0000, addrofs};
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assign spr_addr = du_access ? du_addr : (addrbase | {16'h0000, addrofs});
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//
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//
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// SPR is written by debug unit or by l.mtspr
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// SPR is written by debug unit or by l.mtspr
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//
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//
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assign spr_dat_o = du_write ? du_dat_du : dat_i;
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assign spr_dat_o = du_write ? du_dat_du : dat_i;
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//
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//
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// debug unit data input:
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// debug unit data input:
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// - write into debug unit SPRs by debug unit itself
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// - read of SPRS by debug unit
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// - read of SPRS by debug unit
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// - write into debug unit SPRs by debug unit itself
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// - write into debug unit SPRs by l.mtspr
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// - write into debug unit SPRs by l.mtspr
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//
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//
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assign du_dat_cpu = du_write ? du_dat_du : du_read ? to_wbmux : dat_i;
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assign du_dat_cpu = du_read ? to_wbmux : du_write ? du_dat_du : dat_i;
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//
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//
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// Write into SPRs when l.mtspr
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// Write into SPRs when DU or l.mtspr
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//
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//
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assign spr_we = du_write | write_spr;
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assign spr_we = du_write | ex_spr_write;
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//
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//
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// Qualify chip selects
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// Qualify chip selects
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//
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//
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assign spr_cs = unqualified_cs & {32{read_spr | write_spr}};
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assign spr_cs = unqualified_cs & {32{du_read | du_write | ex_spr_read | (ex_spr_write & sr[`OR1200_SR_SM])}};
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//
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//
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// Decoding of groups
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// Decoding of groups
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//
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//
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always @(spr_addr)
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always @(spr_addr)
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| Line 296... |
Line 303... |
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//
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//
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// What to write into SR
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// What to write into SR
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//
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//
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assign to_sr[`OR1200_SR_FO:`OR1200_SR_OV] =
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assign to_sr[`OR1200_SR_FO:`OR1200_SR_OV] =
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(except_started) ? sr[`OR1200_SR_FO:`OR1200_SR_OV] :
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(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_FO:`OR1200_SR_OV] :
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(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_FO:`OR1200_SR_OV] :
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(write_spr && sr_sel) ? {1'b1, spr_dat_o[`OR1200_SR_FO-1:`OR1200_SR_OV]}:
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(spr_we && sr_sel) ? {1'b1, spr_dat_o[`OR1200_SR_FO-1:`OR1200_SR_OV]}:
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sr[`OR1200_SR_FO:`OR1200_SR_OV];
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sr[`OR1200_SR_FO:`OR1200_SR_OV];
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assign to_sr[`OR1200_SR_TED] =
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(except_started) ? 1'b1 :
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(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_TED] :
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(spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_TED]:
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sr[`OR1200_SR_TED];
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assign to_sr[`OR1200_SR_CY] =
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assign to_sr[`OR1200_SR_CY] =
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(except_started) ? sr[`OR1200_SR_CY] :
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(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CY] :
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(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CY] :
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cy_we ? cyforw :
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cy_we ? cyforw :
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(write_spr && sr_sel) ? spr_dat_o[`OR1200_SR_CY] :
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(spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_CY] :
|
sr[`OR1200_SR_CY];
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sr[`OR1200_SR_CY];
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assign to_sr[`OR1200_SR_F] =
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assign to_sr[`OR1200_SR_F] =
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(except_started) ? sr[`OR1200_SR_F] :
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(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_F] :
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(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_F] :
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flag_we ? flagforw :
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flag_we ? flagforw :
|
(write_spr && sr_sel) ? spr_dat_o[`OR1200_SR_F] :
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(spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_F] :
|
sr[`OR1200_SR_F];
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sr[`OR1200_SR_F];
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assign to_sr[`OR1200_SR_CE:`OR1200_SR_SM] =
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assign to_sr[`OR1200_SR_CE:`OR1200_SR_SM] =
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(except_started) ? {sr[`OR1200_SR_CE:`OR1200_SR_LEE], 2'b00, sr[`OR1200_SR_ICE:`OR1200_SR_DCE], 3'b001} :
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(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CE:`OR1200_SR_SM] :
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(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CE:`OR1200_SR_SM] :
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(write_spr && sr_sel) ? spr_dat_o[`OR1200_SR_CE:`OR1200_SR_SM]:
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(spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_CE:`OR1200_SR_SM]:
|
sr[`OR1200_SR_CE:`OR1200_SR_SM];
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sr[`OR1200_SR_CE:`OR1200_SR_SM];
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//
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//
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// Selects for system SPRs
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// Selects for system SPRs
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//
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//
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| Line 329... |
Line 345... |
assign esr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_ESR));
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assign esr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_ESR));
|
|
|
//
|
//
|
// Write enables for system SPRs
|
// Write enables for system SPRs
|
//
|
//
|
assign sr_we = (write_spr && sr_sel) | (branch_op == `OR1200_BRANCHOP_RFE) | flag_we | cy_we;
|
assign sr_we = (spr_we && sr_sel) | (branch_op == `OR1200_BRANCHOP_RFE) | flag_we | cy_we;
|
assign pc_we = (write_spr && (npc_sel | ppc_sel));
|
assign pc_we = (du_write && (npc_sel | ppc_sel));
|
assign epcr_we = (write_spr && epcr_sel);
|
assign epcr_we = (spr_we && epcr_sel);
|
assign eear_we = (write_spr && eear_sel);
|
assign eear_we = (spr_we && eear_sel);
|
assign esr_we = (write_spr && esr_sel);
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assign esr_we = (spr_we && esr_sel);
|
|
|
//
|
//
|
// Output from system SPRs
|
// Output from system SPRs
|
//
|
//
|
assign sys_data = (spr_dat_cfgr & {32{read_spr & cfgr_sel}}) |
|
assign sys_data = (spr_dat_cfgr & {32{cfgr_sel}}) |
|
(spr_dat_rf & {32{read_spr & rf_sel}}) |
|
(spr_dat_rf & {32{rf_sel}}) |
|
(spr_dat_npc & {32{read_spr & npc_sel}}) |
|
(spr_dat_npc & {32{npc_sel}}) |
|
(spr_dat_ppc & {32{read_spr & ppc_sel}}) |
|
(spr_dat_ppc & {32{ppc_sel}}) |
|
({{32-`OR1200_SR_WIDTH{1'b0}},sr} & {32{read_spr & sr_sel}}) |
|
({{32-`OR1200_SR_WIDTH{1'b0}},sr} & {32{sr_sel}}) |
|
(epcr & {32{read_spr & epcr_sel}}) |
|
(epcr & {32{epcr_sel}}) |
|
(eear & {32{read_spr & eear_sel}}) |
|
(eear & {32{eear_sel}}) |
|
({{32-`OR1200_SR_WIDTH{1'b0}},esr} & {32{read_spr & esr_sel}});
|
({{32-`OR1200_SR_WIDTH{1'b0}},esr} & {32{esr_sel}});
|
|
|
//
|
//
|
// Flag alias
|
// Flag alias
|
//
|
//
|
assign flag = sr[`OR1200_SR_F];
|
assign flag = sr[`OR1200_SR_F];
|
| Line 362... |
Line 378... |
//
|
//
|
// Supervision register
|
// Supervision register
|
//
|
//
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
sr <= #1 {1'b1, `OR1200_SR_EPH_DEF, {`OR1200_SR_WIDTH-3{1'b0}}, 1'b1};
|
sr_reg <= #1 {2'h1, `OR1200_SR_EPH_DEF, {`OR1200_SR_WIDTH-4{1'b0}}, 1'b1};
|
else if (except_started) begin
|
else if (except_started)
|
sr[`OR1200_SR_SM] <= #1 1'b1;
|
sr_reg <= #1 to_sr[`OR1200_SR_WIDTH-1:0];
|
sr[`OR1200_SR_TEE] <= #1 1'b0;
|
|
sr[`OR1200_SR_IEE] <= #1 1'b0;
|
|
sr[`OR1200_SR_DME] <= #1 1'b0;
|
|
sr[`OR1200_SR_IME] <= #1 1'b0;
|
|
end
|
|
else if (sr_we)
|
else if (sr_we)
|
sr <= #1 to_sr[`OR1200_SR_WIDTH-1:0];
|
sr_reg <= #1 to_sr[`OR1200_SR_WIDTH-1:0];
|
|
|
|
// EPH part of Supervision register
|
|
always @(posedge clk or posedge rst)
|
|
// default value
|
|
if (rst) begin
|
|
sr_reg_bit_eph <= #1 `OR1200_SR_EPH_DEF;
|
|
sr_reg_bit_eph_select <= #1 1'b1; // select async. value due to reset state
|
|
end
|
|
// selected value (different from default) is written into FF after reset state
|
|
else if (sr_reg_bit_eph_select) begin
|
|
sr_reg_bit_eph <= #1 boot_adr_sel_i; // dynamic value can only be assigned to FF out of reset!
|
|
sr_reg_bit_eph_select <= #1 1'b0; // select FF value
|
|
end
|
|
else if (sr_we) begin
|
|
sr_reg_bit_eph <= #1 to_sr[`OR1200_SR_EPH];
|
|
end
|
|
|
|
// select async. value of EPH bit after reset
|
|
assign sr_reg_bit_eph_muxed = (sr_reg_bit_eph_select) ? boot_adr_sel_i : sr_reg_bit_eph;
|
|
|
|
// EPH part joined together with rest of Supervision register
|
|
always @(sr_reg or sr_reg_bit_eph_muxed)
|
|
sr = {sr_reg[`OR1200_SR_WIDTH-1:`OR1200_SR_WIDTH-2], sr_reg_bit_eph_muxed, sr_reg[`OR1200_SR_WIDTH-4:0]};
|
|
|
//
|
//
|
// MTSPR/MFSPR interface
|
// MTSPR/MFSPR interface
|
//
|
//
|
always @(sprs_op or spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or
|
always @(spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or
|
spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin
|
spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin
|
case (sprs_op) // synopsys parallel_case
|
|
`OR1200_ALUOP_MTSR : begin
|
|
write_spr = 1'b1;
|
|
read_spr = 1'b0;
|
|
to_wbmux = 32'b0;
|
|
end
|
|
`OR1200_ALUOP_MFSR : begin
|
|
casex (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
|
casex (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
|
|
`OR1200_SPR_GROUP_SYS:
|
|
to_wbmux = sys_data;
|
`OR1200_SPR_GROUP_TT:
|
`OR1200_SPR_GROUP_TT:
|
to_wbmux = spr_dat_tt;
|
to_wbmux = spr_dat_tt;
|
`OR1200_SPR_GROUP_PIC:
|
`OR1200_SPR_GROUP_PIC:
|
to_wbmux = spr_dat_pic;
|
to_wbmux = spr_dat_pic;
|
`OR1200_SPR_GROUP_PM:
|
`OR1200_SPR_GROUP_PM:
|
| Line 398... |
Line 427... |
to_wbmux = spr_dat_dmmu;
|
to_wbmux = spr_dat_dmmu;
|
`OR1200_SPR_GROUP_IMMU:
|
`OR1200_SPR_GROUP_IMMU:
|
to_wbmux = spr_dat_immu;
|
to_wbmux = spr_dat_immu;
|
`OR1200_SPR_GROUP_MAC:
|
`OR1200_SPR_GROUP_MAC:
|
to_wbmux = spr_dat_mac;
|
to_wbmux = spr_dat_mac;
|
`OR1200_SPR_GROUP_DU:
|
default: //`OR1200_SPR_GROUP_DU:
|
to_wbmux = spr_dat_du;
|
to_wbmux = spr_dat_du;
|
`OR1200_SPR_GROUP_SYS:
|
|
to_wbmux = sys_data;
|
|
default:
|
|
to_wbmux = 32'b0;
|
|
endcase
|
|
write_spr = 1'b0;
|
|
read_spr = 1'b1;
|
|
end
|
|
default : begin
|
|
write_spr = 1'b0;
|
|
read_spr = 1'b0;
|
|
to_wbmux = 32'b0;
|
|
end
|
|
endcase
|
endcase
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
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No newline at end of file
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No newline at end of file
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