URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_sprs.v] - Diff between revs 185 and 186

Rev 185	Rev 186
Line 62...	Line 62...
`to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr_we, to_sr, sr,`	`to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr_we, to_sr, sr,`
`spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc, spr_dat_mac,`	`spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc, spr_dat_mac,`
`boot_adr_sel_i,`	`boot_adr_sel_i,`

`// Floating point control register and SPR input`	`// Floating point control register and SPR input`
`fpcsr, fpcsr_we, spr_dat_fpu`	`fpcsr, fpcsr_we, spr_dat_fpu,`

`// From/to other RISC units`	`// From/to other RISC units`
`spr_dat_pic, spr_dat_tt, spr_dat_pm,`	`spr_dat_pic, spr_dat_tt, spr_dat_pm,`
`spr_dat_dmmu, spr_dat_immu, spr_dat_du,`	`spr_dat_dmmu, spr_dat_immu, spr_dat_du,`
`spr_addr, spr_dat_o, spr_cs, spr_we,`	`spr_addr, spr_dat_o, spr_cs, spr_we,`