OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_sprs.v] - Diff between revs 186 and 187

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 186 Rev 187
Line 318... Line 318...
                  (spr_dat_ppc & {32{ppc_sel}}) |
                  (spr_dat_ppc & {32{ppc_sel}}) |
                  ({{32-`OR1200_SR_WIDTH{1'b0}},sr} & {32{sr_sel}}) |
                  ({{32-`OR1200_SR_WIDTH{1'b0}},sr} & {32{sr_sel}}) |
                  (epcr & {32{epcr_sel}}) |
                  (epcr & {32{epcr_sel}}) |
                  (eear & {32{eear_sel}}) |
                  (eear & {32{eear_sel}}) |
`ifdef OR1200_FPU_IMPLEMENTED
`ifdef OR1200_FPU_IMPLEMENTED
                  ({{32-`OR1200_FPCSR_WIDTH{1'b0}},fpcsr} &
                  ({{32-`OR1200_FPCSR_WIDTH{1'b0}},fpcsr} & {32{fpcsr_sel}}) |
                   {32{read_spr & fpcsr_sel}}) |
 
`endif
`endif
                  ({{32-`OR1200_SR_WIDTH{1'b0}},esr} & {32{esr_sel}});
                  ({{32-`OR1200_SR_WIDTH{1'b0}},esr} & {32{esr_sel}});
 
 
//
//
// Flag alias
// Flag alias

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.