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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_top.v] - Diff between revs 10 and 142

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Rev 10 Rev 142
Line 41... Line 41... 
////                                                              ////
 
////                                                              ////
 
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
 
//
 
//
 
// CVS Revision History
 
// CVS Revision History
 
//
 
//
 
// $Log: not supported by cvs2svn $
 
// $Log: or1200_top.v,v $
 
 
 
// Revision 2.0  2010/06/30 11:00:00  ORSoC
 
 
 
// Major update: 
 
 
// Structure reordered. 
 
 
//
 
 
 
// Revision 1.13  2004/06/08 18:17:36  lampret
 
 
 
// Non-functional changes. Coding style fixes.
 
 
 
//
 
// Revision 1.12  2004/04/05 08:29:57  lampret
 
// Revision 1.12  2004/04/05 08:29:57  lampret
 
// Merged branch_qmem into main tree.
 
// Merged branch_qmem into main tree.
 
//
 
//
 
// Revision 1.10.4.9  2004/02/11 01:40:11  lampret
 
// Revision 1.10.4.9  2004/02/11 01:40:11  lampret
 
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
 
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
Line 175... Line 182... 
        // Power Management
 
        // Power Management
 
        pm_cpustall_i,
 
        pm_cpustall_i,
 
        pm_clksd_o, pm_dc_gate_o, pm_ic_gate_o, pm_dmmu_gate_o,
 
        pm_clksd_o, pm_dc_gate_o, pm_ic_gate_o, pm_dmmu_gate_o,
 
        pm_immu_gate_o, pm_tt_gate_o, pm_cpu_gate_o, pm_wakeup_o, pm_lvolt_o
 
        pm_immu_gate_o, pm_tt_gate_o, pm_cpu_gate_o, pm_wakeup_o, pm_lvolt_o
 
 
 
 
 
 
 
,sig_tick
 
 
 
 
 
);
 
);
 
 
 
 
 
parameter dw = `OR1200_OPERAND_WIDTH;
 
parameter dw = `OR1200_OPERAND_WIDTH;
 
parameter aw = `OR1200_OPERAND_WIDTH;
 
parameter aw = `OR1200_OPERAND_WIDTH;
 
parameter ppic_ints = `OR1200_PIC_INTS;
 
parameter ppic_ints = `OR1200_PIC_INTS;
Line 316... Line 325... 
//
 
//
 
// IC to BIU
 
// IC to BIU
 
//
 
//
 
wire    [dw-1:0] icbiu_dat_ic;
 
wire    [dw-1:0] icbiu_dat_ic;
 
wire    [aw-1:0] icbiu_adr_ic;
 
wire    [aw-1:0] icbiu_adr_ic;
 
 
 
wire    [aw-1:0] icbiu_adr_ic_word;
 
wire                    icbiu_cyc_ic;
 
wire                    icbiu_cyc_ic;
 
wire                    icbiu_stb_ic;
 
wire                    icbiu_stb_ic;
 
wire                    icbiu_we_ic;
 
wire                    icbiu_we_ic;
 
wire    [3:0]            icbiu_sel_ic;
 
wire    [3:0]            icbiu_sel_ic;
 
wire    [3:0]            icbiu_tag_ic;
 
wire    [3:0]            icbiu_tag_ic;
Line 328... Line 338... 
wire                    icbiu_ack_biu;
 
wire                    icbiu_ack_biu;
 
wire                    icbiu_err_biu;
 
wire                    icbiu_err_biu;
 
wire    [3:0]            icbiu_tag_biu;
 
wire    [3:0]            icbiu_tag_biu;
 
 
 
 
 
//
 
//
 
 
 
// SR Interface (this signal can be connected to the input pin)
 
 
 
//
 
 
 
wire                    boot_adr_sel = `OR1200_SR_EPH_DEF;
 
 
 
 
 
 
 
//
 
// CPU's SPR access to various RISC units (shared wires)
 
// CPU's SPR access to various RISC units (shared wires)
 
//
 
//
 
wire                    supv;
 
wire                    supv;
 
wire    [aw-1:0] spr_addr;
 
wire    [aw-1:0] spr_addr;
 
wire    [dw-1:0] spr_dat_cpu;
 
wire    [dw-1:0] spr_dat_cpu;
 
wire    [31:0]           spr_cs;
 
wire    [31:0]           spr_cs;
 
wire                    spr_we;
 
wire                    spr_we;
 
 
 
 
 
//
 
//
 
 
 
// SB
 
 
 
//
 
 
 
wire                    sb_en;
 
 
 
 
 
 
 
//
 
// DMMU and CPU
 
// DMMU and CPU
 
//
 
//
 
wire                    dmmu_en;
 
wire                    dmmu_en;
 
wire    [31:0]           spr_dat_dmmu;
 
wire    [31:0]           spr_dat_dmmu;
 
 
 
 
Line 441... Line 461... 
 
 
 
 
//
 
//
 
// CPU and TT
 
// CPU and TT
 
//
 
//
 
wire    [dw-1:0] spr_dat_tt;
 
wire    [dw-1:0] spr_dat_tt;
 
wire                    sig_tick;
 
output wire                     sig_tick; // jb
 
 
 
 
 
//
 
//
 
// Debug port and caches/MMUs
 
// Debug port and caches/MMUs
 
//
 
//
 
wire    [dw-1:0] spr_dat_du;
 
wire    [dw-1:0] spr_dat_du;
 
wire                    du_stall;
 
wire                    du_stall;
 
wire    [dw-1:0] du_addr;
 
wire    [dw-1:0] du_addr;
 
wire    [dw-1:0] du_dat_du;
 
wire    [dw-1:0] du_dat_du;
 
wire                    du_read;
 
wire                    du_read;
 
wire                    du_write;
 
wire                    du_write;
 
wire    [12:0]           du_except;
 
wire    [12:0]           du_except_trig;
 
 
 
wire    [12:0]           du_except_stop;
 
wire    [`OR1200_DU_DSR_WIDTH-1:0]     du_dsr;
 
wire    [`OR1200_DU_DSR_WIDTH-1:0]     du_dsr;
 
 
 
wire    [24:0]           du_dmr1;
 
wire    [dw-1:0] du_dat_cpu;
 
wire    [dw-1:0] du_dat_cpu;
 
 
 
wire    [dw-1:0] du_lsu_store_dat;
 
 
 
wire    [dw-1:0] du_lsu_load_dat;
 
wire                    du_hwbkpt;
 
wire                    du_hwbkpt;
 
 
 
wire                    du_hwbkpt_ls_r = 1'b0;
 
 
 
wire                    flushpipe;
 
wire                    ex_freeze;
 
wire                    ex_freeze;
 
 
 
wire                    wb_freeze;
 
 
 
wire                    id_void;
 
 
 
wire                    ex_void;
 
 
 
wire    [31:0]           id_insn;
 
wire    [31:0]           ex_insn;
 
wire    [31:0]           ex_insn;
 
 
 
wire    [31:0]           wb_insn;
 
wire    [31:0]           id_pc;
 
wire    [31:0]           id_pc;
 
 
 
wire    [31:0]           ex_pc;
 
 
 
wire    [31:0]           wb_pc;
 
wire    [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;
 
wire    [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;
 
wire    [31:0]           spr_dat_npc;
 
wire    [31:0]           spr_dat_npc;
 
wire    [31:0]           rf_dataw;
 
wire    [31:0]           rf_dataw;
 
 
 
wire                    abort_ex;
 
 
 
wire                    abort_mvspr;
 
 
 
 
 
`ifdef OR1200_BIST
 
`ifdef OR1200_BIST
 
//
 
//
 
// RAM BIST
 
// RAM BIST
 
//
 
//
Line 488... Line 522... 
wire  [3:0] dcqmem_tag_qmem;
 
wire  [3:0] dcqmem_tag_qmem;
 
 
 
 
 
//
 
//
 
// Instantiation of Instruction WISHBONE BIU
 
// Instantiation of Instruction WISHBONE BIU
 
//
 
//
 
or1200_iwb_biu iwb_biu(
 
or1200_wb_biu iwb_biu(
 
        // RISC clk, rst and clock control
 
        // RISC clk, rst and clock control
 
        .clk(clk_i),
 
        .clk(clk_i),
 
        .rst(rst_i),
 
        .rst(rst_i),
 
        .clmode(clmode_i),
 
        .clmode(clmode_i),
 
 
 
 
Line 517... Line 551... 
        .wb_bte_o(iwb_bte_o),
 
        .wb_bte_o(iwb_bte_o),
 
`endif
 
`endif
 
 
 
 
 
        // Internal RISC bus
 
        // Internal RISC bus
 
        .biu_dat_i(icbiu_dat_ic),
 
        .biu_dat_i(icbiu_dat_ic),
 
        .biu_adr_i(icbiu_adr_ic),
 
        .biu_adr_i(icbiu_adr_ic_word),
 
        .biu_cyc_i(icbiu_cyc_ic),
 
        .biu_cyc_i(icbiu_cyc_ic),
 
        .biu_stb_i(icbiu_stb_ic),
 
        .biu_stb_i(icbiu_stb_ic),
 
        .biu_we_i(icbiu_we_ic),
 
        .biu_we_i(icbiu_we_ic),
 
        .biu_sel_i(icbiu_sel_ic),
 
        .biu_sel_i(icbiu_sel_ic),
 
        .biu_cab_i(icbiu_cab_ic),
 
        .biu_cab_i(icbiu_cab_ic),
 
        .biu_dat_o(icbiu_dat_biu),
 
        .biu_dat_o(icbiu_dat_biu),
 
        .biu_ack_o(icbiu_ack_biu),
 
        .biu_ack_o(icbiu_ack_biu),
 
        .biu_err_o(icbiu_err_biu)
 
        .biu_err_o(icbiu_err_biu)
 
);
 
);
 
 
 
assign icbiu_adr_ic_word = {icbiu_adr_ic[31:2], 2'h0};
 
 
 
 
 
//
 
//
 
// Instantiation of Data WISHBONE BIU
 
// Instantiation of Data WISHBONE BIU
 
//
 
//
 
or1200_wb_biu dwb_biu(
 
or1200_wb_biu dwb_biu(
Line 597... Line 632... 
        .icpu_adr_o(icpu_adr_immu),
 
        .icpu_adr_o(icpu_adr_immu),
 
        .icpu_tag_o(icpu_tag_immu),
 
        .icpu_tag_o(icpu_tag_immu),
 
        .icpu_rty_o(icpu_rty_immu),
 
        .icpu_rty_o(icpu_rty_immu),
 
        .icpu_err_o(icpu_err_immu),
 
        .icpu_err_o(icpu_err_immu),
 
 
 
 
 
 
 
        // SR Interface
 
 
 
        .boot_adr_sel_i(boot_adr_sel),
 
 
 
 
 
        // SPR access
 
        // SPR access
 
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_IMMU]),
 
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_IMMU]),
 
        .spr_write(spr_we),
 
        .spr_write(spr_we),
 
        .spr_addr(spr_addr),
 
        .spr_addr(spr_addr),
 
        .spr_dat_i(spr_dat_cpu),
 
        .spr_dat_i(spr_dat_cpu),
Line 679... Line 717... 
        .icpu_adr_i(icpu_adr_immu),
 
        .icpu_adr_i(icpu_adr_immu),
 
        .icpu_err_i(icpu_err_immu),
 
        .icpu_err_i(icpu_err_immu),
 
        .icpu_tag_i(icpu_tag_immu),
 
        .icpu_tag_i(icpu_tag_immu),
 
 
 
 
 
        // Connection CPU to external Debug port
 
        // Connection CPU to external Debug port
 
        .ex_freeze(ex_freeze),
 
        .id_void(id_void),
 
 
 
        .id_insn(id_insn),
 
 
 
        .ex_void(ex_void),
 
        .ex_insn(ex_insn),
 
        .ex_insn(ex_insn),
 
 
 
        .ex_freeze(ex_freeze),
 
 
 
        .wb_insn(wb_insn),
 
 
 
        .wb_freeze(wb_freeze),
 
        .id_pc(id_pc),
 
        .id_pc(id_pc),
 
 
 
        .ex_pc(ex_pc),
 
 
 
        .wb_pc(wb_pc),
 
        .branch_op(branch_op),
 
        .branch_op(branch_op),
 
 
 
        .rf_dataw(rf_dataw),
 
 
 
        .ex_flushpipe(flushpipe),
 
        .du_stall(du_stall),
 
        .du_stall(du_stall),
 
        .du_addr(du_addr),
 
        .du_addr(du_addr),
 
        .du_dat_du(du_dat_du),
 
        .du_dat_du(du_dat_du),
 
        .du_read(du_read),
 
        .du_read(du_read),
 
        .du_write(du_write),
 
        .du_write(du_write),
 
 
 
        .du_except_trig(du_except_trig),
 
 
 
        .du_except_stop(du_except_stop),
 
        .du_dsr(du_dsr),
 
        .du_dsr(du_dsr),
 
        .du_except(du_except),
 
        .du_dmr1(du_dmr1),
 
        .du_dat_cpu(du_dat_cpu),
 
 
 
        .du_hwbkpt(du_hwbkpt),
 
        .du_hwbkpt(du_hwbkpt),
 
        .rf_dataw(rf_dataw),
 
        .du_hwbkpt_ls_r(du_hwbkpt_ls_r),
 
 
 
        .du_dat_cpu(du_dat_cpu),
 
 
 
        .du_lsu_store_dat(du_lsu_store_dat),
 
 
 
        .du_lsu_load_dat(du_lsu_load_dat),
 
 
 
        .abort_mvspr(abort_mvspr),
 
 
 
        .abort_ex(abort_ex),
 
 
 
 
 
        // Connection IMMU and CPU internally
 
        // Connection IMMU and CPU internally
 
        .immu_en(immu_en),
 
        .immu_en(immu_en),
 
 
 
 
 
        // Connection QMEM and CPU
 
        // Connection QMEM and CPU
Line 715... Line 767... 
        .dcpu_tag_i(dcpu_tag_dmmu),
 
        .dcpu_tag_i(dcpu_tag_dmmu),
 
 
 
 
 
        // Connection DMMU and CPU internally
 
        // Connection DMMU and CPU internally
 
        .dmmu_en(dmmu_en),
 
        .dmmu_en(dmmu_en),
 
 
 
 
 
 
 
        // SR Interface
 
 
 
        .boot_adr_sel_i(boot_adr_sel),
 
 
 
 
 
 
 
        // SB Enable
 
 
 
        .sb_en(sb_en),
 
 
 
 
 
        // Connection PIC and CPU's EXCEPT
 
        // Connection PIC and CPU's EXCEPT
 
        .sig_int(sig_int),
 
        .sig_int(sig_int),
 
        .sig_tick(sig_tick),
 
        .sig_tick(sig_tick),
 
 
 
 
 
        // SPRs
 
        // SPRs
Line 896... Line 954... 
or1200_sb or1200_sb(
 
or1200_sb or1200_sb(
 
        // RISC clock, reset
 
        // RISC clock, reset
 
        .clk(clk_i),
 
        .clk(clk_i),
 
        .rst(rst_i),
 
        .rst(rst_i),
 
 
 
 
 
 
 
        // Internal RISC bus (SB)
 
 
 
        .sb_en(sb_en),
 
 
 
 
 
        // Internal RISC bus (DC<->SB)
 
        // Internal RISC bus (DC<->SB)
 
        .dcsb_dat_i(dcsb_dat_dc),
 
        .dcsb_dat_i(dcsb_dat_dc),
 
        .dcsb_adr_i(dcsb_adr_dc),
 
        .dcsb_adr_i(dcsb_adr_dc),
 
        .dcsb_cyc_i(dcsb_cyc_dc),
 
        .dcsb_cyc_i(dcsb_cyc_dc),
 
        .dcsb_stb_i(dcsb_stb_dc),
 
        .dcsb_stb_i(dcsb_stb_dc),
Line 939... Line 1000... 
        .ex_freeze(ex_freeze),
 
        .ex_freeze(ex_freeze),
 
        .branch_op(branch_op),
 
        .branch_op(branch_op),
 
        .ex_insn(ex_insn),
 
        .ex_insn(ex_insn),
 
        .id_pc(id_pc),
 
        .id_pc(id_pc),
 
        .du_dsr(du_dsr),
 
        .du_dsr(du_dsr),
 
 
 
        .du_dmr1(du_dmr1),
 
 
 
 
 
        // For Trace buffer
 
        // For Trace buffer
 
        .spr_dat_npc(spr_dat_npc),
 
        .spr_dat_npc(spr_dat_npc),
 
        .rf_dataw(rf_dataw),
 
        .rf_dataw(rf_dataw),
 
 
 
 
Line 951... Line 1013... 
        .du_addr(du_addr),
 
        .du_addr(du_addr),
 
        .du_dat_i(du_dat_cpu),
 
        .du_dat_i(du_dat_cpu),
 
        .du_dat_o(du_dat_du),
 
        .du_dat_o(du_dat_du),
 
        .du_read(du_read),
 
        .du_read(du_read),
 
        .du_write(du_write),
 
        .du_write(du_write),
 
        .du_except(du_except),
 
        .du_except_stop(du_except_stop),
 
        .du_hwbkpt(du_hwbkpt),
 
        .du_hwbkpt(du_hwbkpt),
 
 
 
 
 
        // Access to DU's SPRs
 
        // Access to DU's SPRs
 
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_DU]),
 
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_DU]),
 
        .spr_write(spr_we),
 
        .spr_write(spr_we),

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