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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200 Top Level ////
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//// OR1200 Top Level ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// http://opencores.org/project,or1k ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// OR1200 Top Level ////
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//// OR1200 Top Level ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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// $Log: or1200_top.v,v $
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// $Log: or1200_top.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Major update:
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// Major update:
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// Structure reordered.
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// Structure reordered.
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//
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//
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// Revision 1.13 2004/06/08 18:17:36 lampret
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// Non-functional changes. Coding style fixes.
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//
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// Revision 1.12 2004/04/05 08:29:57 lampret
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// Merged branch_qmem into main tree.
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//
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// Revision 1.10.4.9 2004/02/11 01:40:11 lampret
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// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
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//
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// Revision 1.10.4.8 2004/01/17 21:14:14 simons
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// Errors fixed.
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//
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// Revision 1.10.4.7 2004/01/17 19:06:38 simons
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// Error fixed.
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//
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// Revision 1.10.4.6 2004/01/17 18:39:48 simons
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// Error fixed.
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//
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// Revision 1.10.4.5 2004/01/15 06:46:38 markom
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// interface to debug changed; no more opselect; stb-ack protocol
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//
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// Revision 1.10.4.4 2003/12/09 11:46:49 simons
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// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
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//
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// Revision 1.10.4.3 2003/12/05 00:08:44 lampret
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// Fixed instantiation name.
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//
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// Revision 1.10.4.2 2003/07/11 01:10:35 lampret
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// Added three missing wire declarations. No functional changes.
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//
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// Revision 1.10.4.1 2003/07/08 15:36:37 lampret
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// Added embedded memory QMEM.
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//
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// Revision 1.10 2002/12/08 08:57:56 lampret
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// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.
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//
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// Revision 1.9 2002/10/17 20:04:41 lampret
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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//
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// Revision 1.8 2002/08/18 19:54:22 lampret
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// Added store buffer.
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//
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// Revision 1.7 2002/07/14 22:17:17 lampret
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// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
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//
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// Revision 1.6 2002/03/29 15:16:56 lampret
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// Some of the warnings fixed.
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//
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// Revision 1.5 2002/02/11 04:33:17 lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
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// Revision 1.4 2002/02/01 19:56:55 lampret
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// Fixed combinational loops.
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//
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// Revision 1.3 2002/01/28 01:16:00 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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// Revision 1.2 2002/01/18 07:56:00 lampret
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.13 2001/11/23 08:38:51 lampret
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// Changed DSR/DRR behavior and exception detection.
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//
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// Revision 1.12 2001/11/20 00:57:22 lampret
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// Fixed width of du_except.
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//
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// Revision 1.11 2001/11/18 08:36:28 lampret
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// For GDB changed single stepping and disabled trap exception.
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//
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// Revision 1.10 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.9 2001/10/14 13:12:10 lampret
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// MP3 version.
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//
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// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
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// no message
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//
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// Revision 1.4 2001/08/13 03:36:20 lampret
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// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
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//
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// Revision 1.3 2001/08/09 13:39:33 lampret
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// Major clean-up.
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//
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// Revision 1.2 2001/07/22 03:31:54 lampret
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// Fixed RAM's oen bug. Cache bypass under development.
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//
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// Revision 1.1 2001/07/20 00:46:21 lampret
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// Development version of RTL. Libraries are missing.
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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Line 292... |
wire [31:0] dcpu_dat_qmem;
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wire [31:0] dcpu_dat_qmem;
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wire dcpu_ack_qmem;
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wire dcpu_ack_qmem;
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wire dcpu_rty_qmem;
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wire dcpu_rty_qmem;
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wire dcpu_err_dmmu;
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wire dcpu_err_dmmu;
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wire [3:0] dcpu_tag_dmmu;
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wire [3:0] dcpu_tag_dmmu;
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wire dc_no_writethrough;
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//
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//
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// IMMU and CPU
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// IMMU and CPU
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//
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//
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wire immu_en;
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wire immu_en;
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Line 670... |
.dcpu_dat_i(dcpu_dat_qmem),
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.dcpu_dat_i(dcpu_dat_qmem),
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.dcpu_ack_i(dcpu_ack_qmem),
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.dcpu_ack_i(dcpu_ack_qmem),
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.dcpu_rty_i(dcpu_rty_qmem),
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.dcpu_rty_i(dcpu_rty_qmem),
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.dcpu_err_i(dcpu_err_dmmu),
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.dcpu_err_i(dcpu_err_dmmu),
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.dcpu_tag_i(dcpu_tag_dmmu),
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.dcpu_tag_i(dcpu_tag_dmmu),
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.dc_no_writethrough(dc_no_writethrough),
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// Connection DMMU and CPU internally
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// Connection DMMU and CPU internally
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.dmmu_en(dmmu_en),
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.dmmu_en(dmmu_en),
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// SR Interface
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// SR Interface
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Line 697... |
.spr_dat_dmmu(spr_dat_dmmu),
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.spr_dat_dmmu(spr_dat_dmmu),
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.spr_dat_immu(spr_dat_immu),
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.spr_dat_immu(spr_dat_immu),
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.spr_dat_du(spr_dat_du),
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.spr_dat_du(spr_dat_du),
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.spr_dat_npc(spr_dat_npc),
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.spr_dat_npc(spr_dat_npc),
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.spr_cs(spr_cs),
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.spr_cs(spr_cs),
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.spr_we(spr_we)
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.spr_we(spr_we),
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.mtspr_dc_done(mtspr_dc_done)
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);
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);
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//
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//
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// Instantiation of DMMU
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// Instantiation of DMMU
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//
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//
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Line 770... |
.dcqmem_ack_o(dcqmem_ack_dc),
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.dcqmem_ack_o(dcqmem_ack_dc),
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.dcqmem_rty_o(dcqmem_rty_dc),
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.dcqmem_rty_o(dcqmem_rty_dc),
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.dcqmem_err_o(dcqmem_err_dc),
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.dcqmem_err_o(dcqmem_err_dc),
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.dcqmem_tag_o(dcqmem_tag_dc),
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.dcqmem_tag_o(dcqmem_tag_dc),
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.dc_no_writethrough(dc_no_writethrough),
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// SPR access
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// SPR access
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.spr_cs(spr_cs[`OR1200_SPR_GROUP_DC]),
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.spr_cs(spr_cs[`OR1200_SPR_GROUP_DC]),
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.spr_addr(spr_addr),
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.spr_write(spr_we),
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.spr_write(spr_we),
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.spr_dat_i(spr_dat_cpu),
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.spr_dat_i(spr_dat_cpu),
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.mtspr_dc_done(mtspr_dc_done),
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// DC and BIU
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// DC and BIU
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.dcsb_dat_o(dcsb_dat_dc),
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.dcsb_dat_o(dcsb_dat_dc),
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.dcsb_adr_o(dcsb_adr_dc),
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.dcsb_adr_o(dcsb_adr_dc),
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.dcsb_cyc_o(dcsb_cyc_dc),
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.dcsb_cyc_o(dcsb_cyc_dc),
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