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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_top.v] - Diff between revs 364 and 481

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Rev 364 Rev 481
Line 430... Line 430...
wire  [3:0] dcqmem_tag_qmem;
wire  [3:0] dcqmem_tag_qmem;
 
 
//
//
// Instantiation of Instruction WISHBONE BIU
// Instantiation of Instruction WISHBONE BIU
//
//
or1200_wb_biu iwb_biu(
or1200_wb_biu
 
  #(.bl((1 << (`OR1200_ICLS-2))))
 
  iwb_biu(
        // RISC clk, rst and clock control
        // RISC clk, rst and clock control
        .clk(clk_i),
        .clk(clk_i),
        .rst(rst_i),
        .rst(rst_i),
        .clmode(clmode_i),
        .clmode(clmode_i),
 
 
Line 474... Line 476...
assign icbiu_adr_ic_word = {icbiu_adr_ic[31:2], 2'h0};
assign icbiu_adr_ic_word = {icbiu_adr_ic[31:2], 2'h0};
 
 
//
//
// Instantiation of Data WISHBONE BIU
// Instantiation of Data WISHBONE BIU
//
//
or1200_wb_biu dwb_biu(
or1200_wb_biu
 
  #(.bl((1 << (`OR1200_DCLS-2))))
 
  dwb_biu(
        // RISC clk, rst and clock control
        // RISC clk, rst and clock control
        .clk(clk_i),
        .clk(clk_i),
        .rst(rst_i),
        .rst(rst_i),
        .clmode(clmode_i),
        .clmode(clmode_i),
 
 

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