URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_tpram_32x32.v] - Diff between revs 142 and 258

Rev 142	Rev 258
Line 387...	Line 387...
`//`	`//`
`// RAM write`	`// RAM write`
`//`	`//`
`always @(posedge clk_a)`	`always @(posedge clk_a)`
`if (ce_a && we_a)`	`if (ce_a && we_a)`
`mem[addr_a] <= #1 di_a;`	`mem[addr_a] <= di_a;`

`//`	`//`
`// RAM write`	`// RAM write`
`//`	`//`
`always @(posedge clk_b)`	`always @(posedge clk_b)`
`if (ce_b && we_b)`	`if (ce_b && we_b)`
`mem[addr_b] <= #1 di_b;`	`mem[addr_b] <= di_b;`

`//`	`//`
`// RAM read address register`	`// RAM read address register`
`//`	`//`
`always @(posedge clk_a or posedge rst_a)`	`always @(posedge clk_a or posedge rst_a)`
`if (rst_a)`	`if (rst_a)`
`addr_a_reg <= #1 {aw{1'b0}};`	`addr_a_reg <= {aw{1'b0}};`
`else if (ce_a)`	`else if (ce_a)`
`addr_a_reg <= #1 addr_a;`	`addr_a_reg <= addr_a;`

`//`	`//`
`// RAM read address register`	`// RAM read address register`
`//`	`//`
`always @(posedge clk_b or posedge rst_b)`	`always @(posedge clk_b or posedge rst_b)`
`if (rst_b)`	`if (rst_b)`
`addr_b_reg <= #1 {aw{1'b0}};`	`addr_b_reg <= {aw{1'b0}};`
`else if (ce_b)`	`else if (ce_b)`
`addr_b_reg <= #1 addr_b;`	`addr_b_reg <= addr_b;`

`endif // !OR1200_ALTERA_LPM	`endif // !OR1200_ALTERA_LPM
`endif // !OR1200_XILINX_RAMB16	`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4	`endif // !OR1200_XILINX_RAMB4
`endif // !OR1200_VIRAGE_STP	`endif // !OR1200_VIRAGE_STP