URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_tpram_32x32.v] - Diff between revs 258 and 358

Rev 258	Rev 358
Line 399...	Line 399...
`mem[addr_b] <= di_b;`	`mem[addr_b] <= di_b;`

`//`	`//`
`// RAM read address register`	`// RAM read address register`
`//`	`//`
`always @(posedge clk_a or posedge rst_a)`	always @(posedge clk_a or `OR1200_RST_EVENT rst_a)
`if (rst_a)`	if (rst_a == `OR1200_RST_VALUE)
`addr_a_reg <= {aw{1'b0}};`	`addr_a_reg <= {aw{1'b0}};`
`else if (ce_a)`	`else if (ce_a)`
`addr_a_reg <= addr_a;`	`addr_a_reg <= addr_a;`

`//`	`//`
`// RAM read address register`	`// RAM read address register`
`//`	`//`
`always @(posedge clk_b or posedge rst_b)`	always @(posedge clk_b or `OR1200_RST_EVENT rst_b)
`if (rst_b)`	if (rst_b == `OR1200_RST_VALUE)
`addr_b_reg <= {aw{1'b0}};`	`addr_b_reg <= {aw{1'b0}};`
`else if (ce_b)`	`else if (ce_b)`
`addr_b_reg <= addr_b;`	`addr_b_reg <= addr_b;`

`endif // !OR1200_ALTERA_LPM	`endif // !OR1200_ALTERA_LPM