URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_tt.v] - Diff between revs 142 and 258

Rev 142	Rev 258
Line 153...	Line 153...
`ifdef OR1200_TT_TTMR	`ifdef OR1200_TT_TTMR
`always @(posedge clk or posedge rst)`	`always @(posedge clk or posedge rst)`
`if (rst)`	`if (rst)`
`ttmr <= 32'b0;`	`ttmr <= 32'b0;`
`else if (ttmr_sel && spr_write)`	`else if (ttmr_sel && spr_write)`
`ttmr <= #1 spr_dat_i;`	`ttmr <= spr_dat_i;`
else if (ttmr[`OR1200_TT_TTMR_IE])	else if (ttmr[`OR1200_TT_TTMR_IE])
ttmr[`OR1200_TT_TTMR_IP] <= #1 ttmr[`OR1200_TT_TTMR_IP] \| (match & ttmr[`OR1200_TT_TTMR_IE]);	ttmr[`OR1200_TT_TTMR_IP] <= ttmr[`OR1200_TT_TTMR_IP] \| (match & ttmr[`OR1200_TT_TTMR_IE]);
`else	`else
`assign ttmr = {2'b11, 30'b0}; // TTMR[M] = 0x3`	`assign ttmr = {2'b11, 30'b0}; // TTMR[M] = 0x3`
`endif	`endif

`//`	`//`
Line 168...	Line 168...
`ifdef OR1200_TT_TTCR	`ifdef OR1200_TT_TTCR
`always @(posedge clk or posedge rst)`	`always @(posedge clk or posedge rst)`
`if (rst)`	`if (rst)`
`ttcr <= 32'b0;`	`ttcr <= 32'b0;`
`else if (restart)`	`else if (restart)`
`ttcr <= #1 32'b0;`	`ttcr <= 32'b0;`
`else if (ttcr_sel && spr_write)`	`else if (ttcr_sel && spr_write)`
`ttcr <= #1 spr_dat_i;`	`ttcr <= spr_dat_i;`
`else if (!stop)`	`else if (!stop)`
`ttcr <= #1 ttcr + 32'd1;`	`ttcr <= ttcr + 32'd1;`
`else	`else
`assign ttcr = 32'b0;`	`assign ttcr = 32'b0;`
`endif	`endif

`//`	`//`