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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_tt.v] - Diff between revs 258 and 358

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Rev 258 Rev 358
Line 149... Line 149...
 
 
//
//
// Write to TTMR or update of TTMR[IP] bit
// Write to TTMR or update of TTMR[IP] bit
//
//
`ifdef OR1200_TT_TTMR
`ifdef OR1200_TT_TTMR
always @(posedge clk or posedge rst)
always @(posedge clk or `OR1200_RST_EVENT rst)
        if (rst)
        if (rst == `OR1200_RST_VALUE)
                ttmr <= 32'b0;
                ttmr <= 32'b0;
        else if (ttmr_sel && spr_write)
        else if (ttmr_sel && spr_write)
                ttmr <=  spr_dat_i;
                ttmr <=  spr_dat_i;
        else if (ttmr[`OR1200_TT_TTMR_IE])
        else if (ttmr[`OR1200_TT_TTMR_IE])
                ttmr[`OR1200_TT_TTMR_IP] <=  ttmr[`OR1200_TT_TTMR_IP] | (match & ttmr[`OR1200_TT_TTMR_IE]);
                ttmr[`OR1200_TT_TTMR_IP] <=  ttmr[`OR1200_TT_TTMR_IP] | (match & ttmr[`OR1200_TT_TTMR_IE]);
Line 164... Line 164...
 
 
//
//
// Write to or increment of TTCR
// Write to or increment of TTCR
//
//
`ifdef OR1200_TT_TTCR
`ifdef OR1200_TT_TTCR
always @(posedge clk or posedge rst)
always @(posedge clk or `OR1200_RST_EVENT rst)
        if (rst)
        if (rst == `OR1200_RST_VALUE)
                ttcr <= 32'b0;
                ttcr <= 32'b0;
        else if (restart)
        else if (restart)
                ttcr <=  32'b0;
                ttcr <=  32'b0;
        else if (ttcr_sel && spr_write)
        else if (ttcr_sel && spr_write)
                ttcr <=  spr_dat_i;
                ttcr <=  spr_dat_i;

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