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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's WISHBONE BIU ////
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//// OR1200's WISHBONE BIU ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// http://opencores.org/project,or1k ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Implements WISHBONE interface ////
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//// Implements WISHBONE interface ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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| Line 44... |
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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//
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//
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// $Log: or1200_wb_biu.v,v $
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// $Log: or1200_wb_biu.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Major update:
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// Major update:
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// Structure reordered and bugs fixed.
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// Structure reordered and bugs fixed.
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//
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//
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// Revision 1.7 2004/04/05 08:29:57 lampret
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// Merged branch_qmem into main tree.
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//
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// Revision 1.6.4.1 2003/07/08 15:36:37 lampret
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// Added embedded memory QMEM.
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//
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// Revision 1.6 2003/04/07 20:57:46 lampret
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// Fixed OR1200_CLKDIV_x_SUPPORTED defines. Fixed order of ifdefs.
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//
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// Revision 1.5 2002/12/08 08:57:56 lampret
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// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.
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//
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// Revision 1.4 2002/09/16 03:09:16 lampret
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// Fixed a combinational loop.
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//
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// Revision 1.3 2002/08/12 05:31:37 lampret
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// Added optional retry counter for wb_rty_i. Added graceful termination for aborted transfers.
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//
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// Revision 1.2 2002/07/14 22:17:17 lampret
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// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.12 2001/11/22 13:42:51 lampret
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// Added wb_cyc_o assignment after it was removed by accident.
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//
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// Revision 1.11 2001/11/20 21:28:10 lampret
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// Added optional sampling of inputs.
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//
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// Revision 1.10 2001/11/18 11:32:00 lampret
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// OR1200_REGISTERED_OUTPUTS can now be enabled.
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//
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// Revision 1.9 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.8 2001/10/14 13:12:10 lampret
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// MP3 version.
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//
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// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
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// no message
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//
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// Revision 1.3 2001/08/09 13:39:33 lampret
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// Major clean-up.
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//
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// Revision 1.2 2001/07/22 03:31:54 lampret
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// Fixed RAM's oen bug. Cache bypass under development.
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//
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// Revision 1.1 2001/07/20 00:46:23 lampret
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// Development version of RTL. Libraries are missing.
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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| Line 191... |
Line 138... |
`endif
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`endif
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`ifdef OR1200_WB_B3
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`ifdef OR1200_WB_B3
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reg [2:0] wb_cti_o; // cycle type identifier
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reg [2:0] wb_cti_o; // cycle type identifier
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reg [1:0] wb_bte_o; // burst type extension
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reg [1:0] wb_bte_o; // burst type extension
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`endif
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`endif
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`ifdef OR1200_NO_DC
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reg [dw-1:0] wb_dat_o; // output data bus
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reg [dw-1:0] wb_dat_o; // output data bus
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`else
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assign wb_dat_o = biu_dat_i; // No register on this - straight from DCRAM
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`endif
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`ifdef OR1200_WB_RETRY
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`ifdef OR1200_WB_RETRY
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reg [`OR1200_WB_RETRY-1:0] retry_cnt; // Retry counter
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reg [`OR1200_WB_RETRY-1:0] retry_cnt; // Retry counter
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`else
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`else
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wire retry_cnt = 1'b0;
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wire retry_cnt;
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assign retry_cnt = 1'b0;
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`endif
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`endif
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`ifdef OR1200_WB_B3
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`ifdef OR1200_WB_B3
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reg [1:0] burst_len; // burst counter
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reg [1:0] burst_len; // burst counter
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`endif
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`endif
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| Line 226... |
Line 178... |
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//
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//
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// WISHBONE I/F <-> Internal RISC I/F conversion
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// WISHBONE I/F <-> Internal RISC I/F conversion
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//
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//
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//assign wb_ack = wb_ack_i;
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//assign wb_ack = wb_ack_i;
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assign wb_ack = wb_ack_i && !wb_err_i && !wb_rty_i;
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assign wb_ack = wb_ack_i & !wb_err_i & !wb_rty_i;
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//
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//
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// WB FSM - register part
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// WB FSM - register part
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//
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//
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always @(posedge wb_clk_i or posedge wb_rst_i) begin
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always @(posedge wb_clk_i or posedge wb_rst_i) begin
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if (wb_rst_i)
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if (wb_rst_i)
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wb_fsm_state_cur <= #1 wb_fsm_idle;
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wb_fsm_state_cur <= wb_fsm_idle;
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else
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else
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wb_fsm_state_cur <= #1 wb_fsm_state_nxt;
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wb_fsm_state_cur <= wb_fsm_state_nxt;
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end
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end
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//
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//
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// WB burst tength counter
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// WB burst tength counter
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//
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//
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always @(posedge wb_clk_i or posedge wb_rst_i) begin
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always @(posedge wb_clk_i or posedge wb_rst_i) begin
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if (wb_rst_i) begin
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if (wb_rst_i) begin
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burst_len <= #1 2'h0;
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burst_len <= 2'h0;
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end
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end
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else begin
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else begin
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// burst counter
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// burst counter
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if (wb_fsm_state_cur == wb_fsm_idle)
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if (wb_fsm_state_cur == wb_fsm_idle)
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burst_len <= #1 2'h2;
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burst_len <= 2'h2;
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else if (wb_stb_o && wb_ack)
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else if (wb_stb_o & wb_ack)
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burst_len <= #1 burst_len - 1'b1;
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burst_len <= burst_len - 1'b1;
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end
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end
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end
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end
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//
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//
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// WB FSM - combinatorial part
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// WB FSM - combinatorial part
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//
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//
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always @(wb_fsm_state_cur or burst_len or
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always @(wb_fsm_state_cur or burst_len or wb_err_i or wb_rty_i or wb_ack or
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wb_err_i or wb_rty_i or wb_ack or wb_cti_o or wb_sel_o or wb_stb_o or wb_we_o or
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wb_cti_o or wb_sel_o or wb_stb_o or wb_we_o or biu_cyc_i or
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biu_cyc_i or biu_stb or biu_cab_i or biu_sel_i or biu_we_i) begin
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biu_stb or biu_cab_i or biu_sel_i or biu_we_i) begin
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// States of WISHBONE Finite State Machine
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// States of WISHBONE Finite State Machine
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case(wb_fsm_state_cur)
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case(wb_fsm_state_cur)
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// IDLE
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// IDLE
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wb_fsm_idle : begin
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wb_fsm_idle : begin
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wb_cyc_nxt = biu_cyc_i && biu_stb;
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wb_cyc_nxt = biu_cyc_i & biu_stb;
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wb_stb_nxt = biu_cyc_i && biu_stb;
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wb_stb_nxt = biu_cyc_i & biu_stb;
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wb_cti_nxt = {!biu_cab_i, 1'b1, !biu_cab_i};
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wb_cti_nxt = {!biu_cab_i, 1'b1, !biu_cab_i};
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if (biu_cyc_i && biu_stb)
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if (biu_cyc_i & biu_stb)
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wb_fsm_state_nxt = wb_fsm_trans;
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wb_fsm_state_nxt = wb_fsm_trans;
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else
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else
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wb_fsm_state_nxt = wb_fsm_idle;
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wb_fsm_state_nxt = wb_fsm_idle;
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end
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end
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// normal TRANSFER
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// normal TRANSFER
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wb_fsm_trans : begin
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wb_fsm_trans : begin
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wb_cyc_nxt = !wb_stb_o || !wb_err_i && !wb_rty_i && !(wb_ack && wb_cti_o == 3'b111);
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wb_cyc_nxt = !wb_stb_o | !wb_err_i & !wb_rty_i &
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wb_stb_nxt = !wb_stb_o || !wb_err_i && !wb_rty_i && !wb_ack || !wb_err_i && !wb_rty_i && wb_cti_o == 3'b010 && !wb_we_o;
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!(wb_ack & wb_cti_o == 3'b111);
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wb_cti_nxt[2] = wb_stb_o && wb_ack && burst_len == 'h0 || wb_cti_o[2];
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wb_stb_nxt = !wb_stb_o | !wb_err_i & !wb_rty_i & !wb_ack |
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!wb_err_i & !wb_rty_i & wb_cti_o == 3'b010 /*& !wb_we_o -- Removed to add burst write, JPB*/;
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wb_cti_nxt[2] = wb_stb_o & wb_ack & burst_len == 'h0 | wb_cti_o[2];
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wb_cti_nxt[1] = 1'b1 ;
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wb_cti_nxt[1] = 1'b1 ;
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wb_cti_nxt[0] = wb_stb_o && wb_ack && burst_len == 'h0 || wb_cti_o[0];
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wb_cti_nxt[0] = wb_stb_o & wb_ack & burst_len == 'h0 | wb_cti_o[0];
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//if ((!biu_cyc_i || !biu_stb || !biu_cab_i) && wb_cti_o == 3'b010 || biu_sel_i != wb_sel_o || biu_we_i != wb_we_o)
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if ((!biu_cyc_i || !biu_stb || !biu_cab_i || biu_sel_i != wb_sel_o || biu_we_i != wb_we_o) && wb_cti_o == 3'b010)
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//if ((!biu_cyc_i | !biu_stb | !biu_cab_i) & wb_cti_o == 3'b010 |
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// biu_sel_i != wb_sel_o | biu_we_i != wb_we_o)
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if ((!biu_cyc_i | !biu_stb | !biu_cab_i | biu_sel_i != wb_sel_o |
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biu_we_i != wb_we_o) & wb_cti_o == 3'b010)
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wb_fsm_state_nxt = wb_fsm_last;
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wb_fsm_state_nxt = wb_fsm_last;
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else if ((wb_err_i || wb_rty_i || wb_ack && wb_cti_o == 3'b111) && wb_stb_o)
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else if ((wb_err_i | wb_rty_i | wb_ack & wb_cti_o==3'b111) &
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wb_stb_o)
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wb_fsm_state_nxt = wb_fsm_idle;
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wb_fsm_state_nxt = wb_fsm_idle;
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else
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else
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wb_fsm_state_nxt = wb_fsm_trans;
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wb_fsm_state_nxt = wb_fsm_trans;
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end
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end
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// LAST transfer
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// LAST transfer
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wb_fsm_last : begin
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wb_fsm_last : begin
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wb_cyc_nxt = !wb_stb_o || !wb_err_i && !wb_rty_i && !(wb_ack && wb_cti_o == 3'b111);
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wb_cyc_nxt = !wb_stb_o | !wb_err_i & !wb_rty_i &
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wb_stb_nxt = !wb_stb_o || !wb_err_i && !wb_rty_i && !(wb_ack && wb_cti_o == 3'b111);
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!(wb_ack & wb_cti_o == 3'b111);
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wb_cti_nxt[2] = wb_ack && wb_stb_o || wb_cti_o[2];
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wb_stb_nxt = !wb_stb_o | !wb_err_i & !wb_rty_i &
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!(wb_ack & wb_cti_o == 3'b111);
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wb_cti_nxt[2] = wb_ack & wb_stb_o | wb_cti_o[2];
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wb_cti_nxt[1] = 1'b1 ;
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wb_cti_nxt[1] = 1'b1 ;
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wb_cti_nxt[0] = wb_ack && wb_stb_o || wb_cti_o[0];
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wb_cti_nxt[0] = wb_ack & wb_stb_o | wb_cti_o[0];
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if ((wb_err_i || wb_rty_i || wb_ack && wb_cti_o == 3'b111) && wb_stb_o)
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if ((wb_err_i | wb_rty_i | wb_ack & wb_cti_o == 3'b111) & wb_stb_o)
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wb_fsm_state_nxt = wb_fsm_idle;
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wb_fsm_state_nxt = wb_fsm_idle;
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else
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else
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wb_fsm_state_nxt = wb_fsm_last;
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wb_fsm_state_nxt = wb_fsm_last;
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end
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end
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// default state
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// default state
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| Line 314... |
Line 277... |
//
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//
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// WB FSM - output signals
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// WB FSM - output signals
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//
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//
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always @(posedge wb_clk_i or posedge wb_rst_i) begin
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always @(posedge wb_clk_i or posedge wb_rst_i) begin
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if (wb_rst_i) begin
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if (wb_rst_i) begin
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wb_cyc_o <= #1 1'b0;
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wb_cyc_o <= 1'b0;
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wb_stb_o <= #1 1'b0;
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wb_stb_o <= 1'b0;
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wb_cti_o <= #1 3'b111;
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wb_cti_o <= 3'b111;
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wb_bte_o <= #1 2'b01; // 4-beat wrap burst = constant
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wb_bte_o <= 2'b01; // 4-beat wrap burst = constant
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`ifdef OR1200_WB_CAB
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`ifdef OR1200_WB_CAB
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wb_cab_o <= #1 1'b0;
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wb_cab_o <= 1'b0;
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`endif
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wb_we_o <= 1'b0;
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wb_sel_o <= 4'hf;
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wb_adr_o <= {aw{1'b0}};
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`ifdef OR1200_NO_DC
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wb_dat_o <= {dw{1'b0}};
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`endif
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`endif
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wb_we_o <= #1 1'b0;
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wb_sel_o <= #1 4'hf;
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wb_adr_o <= #1 {aw{1'b0}};
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wb_dat_o <= #1 {dw{1'b0}};
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end
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end
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else begin
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else begin
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wb_cyc_o <= #1 wb_cyc_nxt;
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wb_cyc_o <= wb_cyc_nxt;
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// wb_stb_o <= #1 wb_stb_nxt;
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// wb_stb_o <= wb_stb_nxt;
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if (wb_ack && wb_cti_o == 3'b111)
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if (wb_ack & wb_cti_o == 3'b111)
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wb_stb_o <= #1 1'b0;
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wb_stb_o <= 1'b0;
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else
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else
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wb_stb_o <= #1 wb_stb_nxt;
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wb_stb_o <= wb_stb_nxt;
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wb_cti_o <= #1 wb_cti_nxt;
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wb_cti_o <= wb_cti_nxt;
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wb_bte_o <= #1 2'b01; // 4-beat wrap burst = constant
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wb_bte_o <= 2'b01; // 4-beat wrap burst = constant
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`ifdef OR1200_WB_CAB
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`ifdef OR1200_WB_CAB
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wb_cab_o <= #1 biu_cab_i;
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wb_cab_o <= biu_cab_i;
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`endif
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`endif
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// we and sel - set at beginning of access
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// we and sel - set at beginning of access
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if (wb_fsm_state_cur == wb_fsm_idle) begin
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if (wb_fsm_state_cur == wb_fsm_idle) begin
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wb_we_o <= #1 biu_we_i;
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wb_we_o <= biu_we_i;
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wb_sel_o <= #1 biu_sel_i;
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wb_sel_o <= biu_sel_i;
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end
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end
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// adr - set at beginning of access and changed at every termination
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// adr - set at beginning of access and changed at every termination
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if (wb_fsm_state_cur == wb_fsm_idle) begin
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if (wb_fsm_state_cur == wb_fsm_idle) begin
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wb_adr_o <= #1 biu_adr_i;
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wb_adr_o <= biu_adr_i;
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end
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end
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else if (wb_stb_o && wb_ack) begin
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else if (wb_stb_o & wb_ack) begin
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wb_adr_o[3:2] <= #1 wb_adr_o[3:2] + 1'b1;
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wb_adr_o[3:2] <= wb_adr_o[3:2] + 1'b1;
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end
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end
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`ifdef OR1200_NO_DC
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// dat - write data changed after avery subsequent write access
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// dat - write data changed after avery subsequent write access
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if (!wb_stb_o) begin
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if (!wb_stb_o) begin
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wb_dat_o <= #1 biu_dat_i;
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wb_dat_o <= biu_dat_i;
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end
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end
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`endif
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end
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end
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end
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end
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//
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//
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// WB & BIU termination toggle counters
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// WB & BIU termination toggle counters
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//
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//
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always @(posedge wb_clk_i or posedge wb_rst_i) begin
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always @(posedge wb_clk_i or posedge wb_rst_i) begin
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if (wb_rst_i) begin
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if (wb_rst_i) begin
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wb_ack_cnt <= #1 1'b0;
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wb_ack_cnt <= 1'b0;
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wb_err_cnt <= #1 1'b0;
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wb_err_cnt <= 1'b0;
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wb_rty_cnt <= #1 1'b0;
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wb_rty_cnt <= 1'b0;
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end
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end
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else begin
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else begin
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// WB ack toggle counter
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// WB ack toggle counter
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if (wb_fsm_state_cur == wb_fsm_idle || !clmode)
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if (wb_fsm_state_cur == wb_fsm_idle | !clmode)
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wb_ack_cnt <= #1 1'b0;
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wb_ack_cnt <= 1'b0;
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else if (wb_stb_o && wb_ack)
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else if (wb_stb_o & wb_ack)
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wb_ack_cnt <= #1 !wb_ack_cnt;
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wb_ack_cnt <= !wb_ack_cnt;
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// WB err toggle counter
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// WB err toggle counter
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if (wb_fsm_state_cur == wb_fsm_idle || !clmode)
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if (wb_fsm_state_cur == wb_fsm_idle | !clmode)
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wb_err_cnt <= #1 1'b0;
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wb_err_cnt <= 1'b0;
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else if (wb_stb_o && wb_err_i)
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else if (wb_stb_o & wb_err_i)
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wb_err_cnt <= #1 !wb_err_cnt;
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wb_err_cnt <= !wb_err_cnt;
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// WB rty toggle counter
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// WB rty toggle counter
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if (wb_fsm_state_cur == wb_fsm_idle || !clmode)
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if (wb_fsm_state_cur == wb_fsm_idle | !clmode)
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wb_rty_cnt <= #1 1'b0;
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wb_rty_cnt <= 1'b0;
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else if (wb_stb_o && wb_rty_i)
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else if (wb_stb_o & wb_rty_i)
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wb_rty_cnt <= #1 !wb_rty_cnt;
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wb_rty_cnt <= !wb_rty_cnt;
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end
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end
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end
|
end
|
|
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
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if (rst) begin
|
if (rst) begin
|
biu_stb_reg <= #1 1'b0;
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biu_stb_reg <= 1'b0;
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biu_ack_cnt <= #1 1'b0;
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biu_ack_cnt <= 1'b0;
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biu_err_cnt <= #1 1'b0;
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biu_err_cnt <= 1'b0;
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biu_rty_cnt <= #1 1'b0;
|
biu_rty_cnt <= 1'b0;
|
`ifdef OR1200_WB_RETRY
|
`ifdef OR1200_WB_RETRY
|
retry_cnt <= {`OR1200_WB_RETRY{1'b0}};
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retry_cnt <= {`OR1200_WB_RETRY{1'b0}};
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`endif
|
`endif
|
end
|
end
|
else begin
|
else begin
|
// BIU strobe
|
// BIU strobe
|
if (biu_stb_i && !biu_cab_i && biu_ack_o)
|
if (biu_stb_i & !biu_cab_i & biu_ack_o)
|
biu_stb_reg <= #1 1'b0;
|
biu_stb_reg <= 1'b0;
|
else
|
else
|
biu_stb_reg <= #1 biu_stb_i;
|
biu_stb_reg <= biu_stb_i;
|
// BIU ack toggle counter
|
// BIU ack toggle counter
|
if (wb_fsm_state_cur == wb_fsm_idle || !clmode)
|
if (wb_fsm_state_cur == wb_fsm_idle | !clmode)
|
biu_ack_cnt <= #1 1'b0 ;
|
biu_ack_cnt <= 1'b0 ;
|
else if (biu_ack_o)
|
else if (biu_ack_o)
|
biu_ack_cnt <= #1 !biu_ack_cnt ;
|
biu_ack_cnt <= !biu_ack_cnt ;
|
// BIU err toggle counter
|
// BIU err toggle counter
|
if (wb_fsm_state_cur == wb_fsm_idle || !clmode)
|
if (wb_fsm_state_cur == wb_fsm_idle | !clmode)
|
biu_err_cnt <= #1 1'b0 ;
|
biu_err_cnt <= 1'b0 ;
|
else if (wb_err_i && biu_err_o)
|
else if (wb_err_i & biu_err_o)
|
biu_err_cnt <= #1 !biu_err_cnt ;
|
biu_err_cnt <= !biu_err_cnt ;
|
// BIU rty toggle counter
|
// BIU rty toggle counter
|
if (wb_fsm_state_cur == wb_fsm_idle || !clmode)
|
if (wb_fsm_state_cur == wb_fsm_idle | !clmode)
|
biu_rty_cnt <= #1 1'b0 ;
|
biu_rty_cnt <= 1'b0 ;
|
else if (biu_rty)
|
else if (biu_rty)
|
biu_rty_cnt <= #1 !biu_rty_cnt ;
|
biu_rty_cnt <= !biu_rty_cnt ;
|
`ifdef OR1200_WB_RETRY
|
`ifdef OR1200_WB_RETRY
|
if (biu_ack_o || biu_err_o)
|
if (biu_ack_o | biu_err_o)
|
retry_cnt <= #1 {`OR1200_WB_RETRY{1'b0}};
|
retry_cnt <= {`OR1200_WB_RETRY{1'b0}};
|
else if (biu_rty)
|
else if (biu_rty)
|
retry_cnt <= #1 retry_cnt + 1'b1;
|
retry_cnt <= retry_cnt + 1'b1;
|
`endif
|
`endif
|
end
|
end
|
end
|
end
|
|
|
assign biu_stb = biu_stb_i && biu_stb_reg;
|
assign biu_stb = biu_stb_i & biu_stb_reg;
|
|
|
//
|
//
|
// Input BIU data bus
|
// Input BIU data bus
|
//
|
//
|
assign biu_dat_o = wb_dat_i;
|
assign biu_dat_o = wb_dat_i;
|
|
|
//
|
//
|
// Input BIU termination signals
|
// Input BIU termination signals
|
//
|
//
|
assign biu_rty = (wb_fsm_state_cur == wb_fsm_trans) && wb_rty_i && wb_stb_o && (wb_rty_cnt ~^ biu_rty_cnt);
|
assign biu_rty = (wb_fsm_state_cur == wb_fsm_trans) & wb_rty_i & wb_stb_o & (wb_rty_cnt ~^ biu_rty_cnt);
|
assign biu_ack_o = (wb_fsm_state_cur == wb_fsm_trans) && wb_ack && wb_stb_o && (wb_ack_cnt ~^ biu_ack_cnt);
|
assign biu_ack_o = (wb_fsm_state_cur == wb_fsm_trans) & wb_ack & wb_stb_o & (wb_ack_cnt ~^ biu_ack_cnt);
|
assign biu_err_o = (wb_fsm_state_cur == wb_fsm_trans) && wb_err_i && wb_stb_o && (wb_err_cnt ~^ biu_err_cnt)
|
assign biu_err_o = (wb_fsm_state_cur == wb_fsm_trans) & wb_err_i & wb_stb_o & (wb_err_cnt ~^ biu_err_cnt)
|
`ifdef OR1200_WB_RETRY
|
`ifdef OR1200_WB_RETRY
|
|| biu_rty && retry_cnt[`OR1200_WB_RETRY-1];
|
| biu_rty & retry_cnt[`OR1200_WB_RETRY-1];
|
`else
|
`else
|
;
|
;
|
`endif
|
`endif
|
|
|
|
|
