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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_wb_biu.v] - Diff between revs 258 and 358

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Rev 258	Rev 358
Line 183...	Line 183...
`assign wb_ack = wb_ack_i & !wb_err_i & !wb_rty_i;`	`assign wb_ack = wb_ack_i & !wb_err_i & !wb_rty_i;`

`//`	`//`
`// WB FSM - register part`	`// WB FSM - register part`
`//`	`//`
`always @(posedge wb_clk_i or posedge wb_rst_i) begin`	always @(posedge wb_clk_i or `OR1200_RST_EVENT wb_rst_i) begin
`if (wb_rst_i)`	if (wb_rst_i == `OR1200_RST_VALUE)
`wb_fsm_state_cur <= wb_fsm_idle;`	`wb_fsm_state_cur <= wb_fsm_idle;`
`else`	`else`
`wb_fsm_state_cur <= wb_fsm_state_nxt;`	`wb_fsm_state_cur <= wb_fsm_state_nxt;`
`end`	`end`

`//`	`//`
`// WB burst tength counter`	`// WB burst tength counter`
`//`	`//`
`always @(posedge wb_clk_i or posedge wb_rst_i) begin`	always @(posedge wb_clk_i or `OR1200_RST_EVENT wb_rst_i) begin
`if (wb_rst_i) begin`	if (wb_rst_i == `OR1200_RST_VALUE) begin
`burst_len <= 2'h0;`	`burst_len <= 2'h0;`
`end`	`end`
`else begin`	`else begin`
`// burst counter`	`// burst counter`
`if (wb_fsm_state_cur == wb_fsm_idle)`	`if (wb_fsm_state_cur == wb_fsm_idle)`
Line 275...	Line 275...
`end`	`end`

`//`	`//`
`// WB FSM - output signals`	`// WB FSM - output signals`
`//`	`//`
`always @(posedge wb_clk_i or posedge wb_rst_i) begin`	always @(posedge wb_clk_i or `OR1200_RST_EVENT wb_rst_i) begin
`if (wb_rst_i) begin`	if (wb_rst_i == `OR1200_RST_VALUE) begin
`wb_cyc_o <= 1'b0;`	`wb_cyc_o <= 1'b0;`
`wb_stb_o <= 1'b0;`	`wb_stb_o <= 1'b0;`
`wb_cti_o <= 3'b111;`	`wb_cti_o <= 3'b111;`
`wb_bte_o <= 2'b01; // 4-beat wrap burst = constant`	`wb_bte_o <= 2'b01; // 4-beat wrap burst = constant`
`ifdef OR1200_WB_CAB	`ifdef OR1200_WB_CAB
Line 327...	Line 327...
`end`	`end`

`//`	`//`
`// WB & BIU termination toggle counters`	`// WB & BIU termination toggle counters`
`//`	`//`
`always @(posedge wb_clk_i or posedge wb_rst_i) begin`	always @(posedge wb_clk_i or `OR1200_RST_EVENT wb_rst_i) begin
`if (wb_rst_i) begin`	if (wb_rst_i == `OR1200_RST_VALUE) begin
`wb_ack_cnt <= 1'b0;`	`wb_ack_cnt <= 1'b0;`
`wb_err_cnt <= 1'b0;`	`wb_err_cnt <= 1'b0;`
`wb_rty_cnt <= 1'b0;`	`wb_rty_cnt <= 1'b0;`
`end`	`end`
`else begin`	`else begin`
Line 352...	Line 352...
`else if (wb_stb_o & wb_rty_i)`	`else if (wb_stb_o & wb_rty_i)`
`wb_rty_cnt <= !wb_rty_cnt;`	`wb_rty_cnt <= !wb_rty_cnt;`
`end`	`end`
`end`	`end`

`always @(posedge clk or posedge rst) begin`	always @(posedge clk or `OR1200_RST_EVENT rst) begin
`if (rst) begin`	if (rst == `OR1200_RST_VALUE) begin
`biu_stb_reg <= 1'b0;`	`biu_stb_reg <= 1'b0;`
`biu_ack_cnt <= 1'b0;`	`biu_ack_cnt <= 1'b0;`
`biu_err_cnt <= 1'b0;`	`biu_err_cnt <= 1'b0;`
`biu_rty_cnt <= 1'b0;`	`biu_rty_cnt <= 1'b0;`
`ifdef OR1200_WB_RETRY	`ifdef OR1200_WB_RETRY

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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_wb_biu.v] - Diff between revs 258 and 358