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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_wb_biu.v] - Diff between revs 142 and 258

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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  OR1200's WISHBONE BIU                                       ////
////  OR1200's WISHBONE BIU                                       ////
////                                                              ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////  http://opencores.org/project,or1k                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Implements WISHBONE interface                               ////
////  Implements WISHBONE interface                               ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
Line 44... Line 44...
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
 
//
//
// $Log: or1200_wb_biu.v,v $
// $Log: or1200_wb_biu.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Major update: 
// Major update: 
// Structure reordered and bugs fixed. 
// Structure reordered and bugs fixed. 
//
//
// Revision 1.7  2004/04/05 08:29:57  lampret
 
// Merged branch_qmem into main tree.
 
//
 
// Revision 1.6.4.1  2003/07/08 15:36:37  lampret
 
// Added embedded memory QMEM.
 
//
 
// Revision 1.6  2003/04/07 20:57:46  lampret
 
// Fixed OR1200_CLKDIV_x_SUPPORTED defines. Fixed order of ifdefs.
 
//
 
// Revision 1.5  2002/12/08 08:57:56  lampret
 
// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.
 
//
 
// Revision 1.4  2002/09/16 03:09:16  lampret
 
// Fixed a combinational loop.
 
//
 
// Revision 1.3  2002/08/12 05:31:37  lampret
 
// Added optional retry counter for wb_rty_i. Added graceful termination for aborted transfers.
 
//
 
// Revision 1.2  2002/07/14 22:17:17  lampret
 
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
 
//
 
// Revision 1.1  2002/01/03 08:16:15  lampret
 
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
 
//
 
// Revision 1.12  2001/11/22 13:42:51  lampret
 
// Added wb_cyc_o assignment after it was removed by accident.
 
//
 
// Revision 1.11  2001/11/20 21:28:10  lampret
 
// Added optional sampling of inputs.
 
//
 
// Revision 1.10  2001/11/18 11:32:00  lampret
 
// OR1200_REGISTERED_OUTPUTS can now be enabled.
 
//
 
// Revision 1.9  2001/10/21 17:57:16  lampret
 
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
 
//
 
// Revision 1.8  2001/10/14 13:12:10  lampret
 
// MP3 version.
 
//
 
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
 
// no message
 
//
 
// Revision 1.3  2001/08/09 13:39:33  lampret
 
// Major clean-up.
 
//
 
// Revision 1.2  2001/07/22 03:31:54  lampret
 
// Fixed RAM's oen bug. Cache bypass under development.
 
//
 
// Revision 1.1  2001/07/20 00:46:23  lampret
 
// Development version of RTL. Libraries are missing.
 
//
 
//
 
 
 
// synopsys translate_off
// synopsys translate_off
`include "timescale.v"
`include "timescale.v"
// synopsys translate_on
// synopsys translate_on
`include "or1200_defines.v"
`include "or1200_defines.v"
Line 191... Line 138...
`endif
`endif
`ifdef OR1200_WB_B3
`ifdef OR1200_WB_B3
reg     [2:0]                    wb_cti_o;       // cycle type identifier
reg     [2:0]                    wb_cti_o;       // cycle type identifier
reg     [1:0]                    wb_bte_o;       // burst type extension
reg     [1:0]                    wb_bte_o;       // burst type extension
`endif
`endif
 
`ifdef OR1200_NO_DC
reg     [dw-1:0]         wb_dat_o;       // output data bus
reg     [dw-1:0]         wb_dat_o;       // output data bus
 
`else
 
   assign wb_dat_o = biu_dat_i;    // No register on this - straight from DCRAM
 
`endif
 
 
`ifdef OR1200_WB_RETRY
`ifdef OR1200_WB_RETRY
reg     [`OR1200_WB_RETRY-1:0]   retry_cnt;      // Retry counter
reg     [`OR1200_WB_RETRY-1:0]   retry_cnt;      // Retry counter
`else
`else
wire                            retry_cnt       = 1'b0;
   wire                                 retry_cnt;
 
   assign retry_cnt = 1'b0;
`endif
`endif
`ifdef OR1200_WB_B3
`ifdef OR1200_WB_B3
reg     [1:0]                    burst_len;      // burst counter
reg     [1:0]                    burst_len;      // burst counter
`endif
`endif
 
 
Line 226... Line 178...
 
 
//
//
// WISHBONE I/F <-> Internal RISC I/F conversion
// WISHBONE I/F <-> Internal RISC I/F conversion
//
//
//assign wb_ack = wb_ack_i;
//assign wb_ack = wb_ack_i;
assign wb_ack = wb_ack_i && !wb_err_i && !wb_rty_i;
   assign wb_ack = wb_ack_i & !wb_err_i & !wb_rty_i;
 
 
//
//
// WB FSM - register part
// WB FSM - register part
// 
// 
always @(posedge wb_clk_i or posedge wb_rst_i) begin
always @(posedge wb_clk_i or posedge wb_rst_i) begin
        if (wb_rst_i)
        if (wb_rst_i)
                wb_fsm_state_cur <= #1 wb_fsm_idle;
        wb_fsm_state_cur <=  wb_fsm_idle;
        else
        else
                wb_fsm_state_cur <= #1 wb_fsm_state_nxt;
        wb_fsm_state_cur <=  wb_fsm_state_nxt;
end
end
 
 
//
//
// WB burst tength counter
// WB burst tength counter
// 
// 
always @(posedge wb_clk_i or posedge wb_rst_i) begin
always @(posedge wb_clk_i or posedge wb_rst_i) begin
        if (wb_rst_i) begin
        if (wb_rst_i) begin
                burst_len <= #1 2'h0;
         burst_len <=  2'h0;
        end
        end
        else begin
        else begin
                // burst counter
                // burst counter
                if (wb_fsm_state_cur == wb_fsm_idle)
                if (wb_fsm_state_cur == wb_fsm_idle)
                        burst_len <= #1 2'h2;
           burst_len <=  2'h2;
                else if (wb_stb_o && wb_ack)
         else if (wb_stb_o & wb_ack)
                        burst_len <= #1 burst_len - 1'b1;
           burst_len <=  burst_len - 1'b1;
        end
        end
end
end
 
 
// 
// 
// WB FSM - combinatorial part
// WB FSM - combinatorial part
// 
// 
always @(wb_fsm_state_cur or burst_len or
   always @(wb_fsm_state_cur or burst_len or wb_err_i or wb_rty_i or wb_ack or
         wb_err_i or wb_rty_i or wb_ack or wb_cti_o or wb_sel_o or wb_stb_o or wb_we_o or
            wb_cti_o or wb_sel_o or wb_stb_o or wb_we_o or biu_cyc_i or
         biu_cyc_i or biu_stb or biu_cab_i or biu_sel_i or biu_we_i) begin
            biu_stb or biu_cab_i or biu_sel_i or biu_we_i) begin
// States of WISHBONE Finite State Machine
// States of WISHBONE Finite State Machine
        case(wb_fsm_state_cur)
        case(wb_fsm_state_cur)
        // IDLE 
        // IDLE 
        wb_fsm_idle : begin
        wb_fsm_idle : begin
                wb_cyc_nxt = biu_cyc_i && biu_stb;
           wb_cyc_nxt = biu_cyc_i & biu_stb;
                wb_stb_nxt = biu_cyc_i && biu_stb;
           wb_stb_nxt = biu_cyc_i & biu_stb;
                wb_cti_nxt = {!biu_cab_i, 1'b1, !biu_cab_i};
                wb_cti_nxt = {!biu_cab_i, 1'b1, !biu_cab_i};
                if (biu_cyc_i && biu_stb)
           if (biu_cyc_i & biu_stb)
                        wb_fsm_state_nxt = wb_fsm_trans;
                        wb_fsm_state_nxt = wb_fsm_trans;
                else
                else
                        wb_fsm_state_nxt = wb_fsm_idle;
                        wb_fsm_state_nxt = wb_fsm_idle;
        end
        end
        // normal TRANSFER
        // normal TRANSFER
        wb_fsm_trans : begin
        wb_fsm_trans : begin
                wb_cyc_nxt = !wb_stb_o || !wb_err_i && !wb_rty_i && !(wb_ack && wb_cti_o == 3'b111);
           wb_cyc_nxt = !wb_stb_o | !wb_err_i & !wb_rty_i &
                wb_stb_nxt = !wb_stb_o || !wb_err_i && !wb_rty_i && !wb_ack || !wb_err_i && !wb_rty_i && wb_cti_o == 3'b010 && !wb_we_o;
                        !(wb_ack & wb_cti_o == 3'b111);
                wb_cti_nxt[2] = wb_stb_o && wb_ack && burst_len == 'h0 || wb_cti_o[2];
 
 
           wb_stb_nxt = !wb_stb_o | !wb_err_i & !wb_rty_i & !wb_ack |
 
                        !wb_err_i & !wb_rty_i & wb_cti_o == 3'b010 /*& !wb_we_o -- Removed to add burst write, JPB*/;
 
 
 
           wb_cti_nxt[2] = wb_stb_o & wb_ack & burst_len == 'h0 | wb_cti_o[2];
                wb_cti_nxt[1] = 1'b1  ;
                wb_cti_nxt[1] = 1'b1  ;
                wb_cti_nxt[0] = wb_stb_o && wb_ack && burst_len == 'h0 || wb_cti_o[0];
           wb_cti_nxt[0] = wb_stb_o & wb_ack & burst_len == 'h0 | wb_cti_o[0];
                //if ((!biu_cyc_i || !biu_stb || !biu_cab_i) && wb_cti_o == 3'b010  || biu_sel_i != wb_sel_o || biu_we_i != wb_we_o)
 
                if ((!biu_cyc_i || !biu_stb || !biu_cab_i || biu_sel_i != wb_sel_o || biu_we_i != wb_we_o) && wb_cti_o == 3'b010)
           //if ((!biu_cyc_i | !biu_stb | !biu_cab_i) & wb_cti_o == 3'b010  | 
 
           //     biu_sel_i != wb_sel_o | biu_we_i != wb_we_o)
 
 
 
           if ((!biu_cyc_i | !biu_stb | !biu_cab_i | biu_sel_i != wb_sel_o |
 
                biu_we_i != wb_we_o) & wb_cti_o == 3'b010)
                        wb_fsm_state_nxt = wb_fsm_last;
                        wb_fsm_state_nxt = wb_fsm_last;
                else if ((wb_err_i || wb_rty_i || wb_ack && wb_cti_o == 3'b111) && wb_stb_o)
           else if ((wb_err_i | wb_rty_i | wb_ack & wb_cti_o==3'b111) &
 
                    wb_stb_o)
                        wb_fsm_state_nxt = wb_fsm_idle;
                        wb_fsm_state_nxt = wb_fsm_idle;
                else
                else
                        wb_fsm_state_nxt = wb_fsm_trans;
                        wb_fsm_state_nxt = wb_fsm_trans;
        end
        end
        // LAST transfer
        // LAST transfer
        wb_fsm_last : begin
        wb_fsm_last : begin
                wb_cyc_nxt = !wb_stb_o || !wb_err_i && !wb_rty_i && !(wb_ack && wb_cti_o == 3'b111);
           wb_cyc_nxt = !wb_stb_o | !wb_err_i & !wb_rty_i &
                wb_stb_nxt = !wb_stb_o || !wb_err_i && !wb_rty_i && !(wb_ack && wb_cti_o == 3'b111);
                        !(wb_ack & wb_cti_o == 3'b111);
                wb_cti_nxt[2] = wb_ack && wb_stb_o || wb_cti_o[2];
           wb_stb_nxt = !wb_stb_o | !wb_err_i & !wb_rty_i &
 
                        !(wb_ack & wb_cti_o == 3'b111);
 
           wb_cti_nxt[2] = wb_ack & wb_stb_o | wb_cti_o[2];
                wb_cti_nxt[1] = 1'b1                  ;
                wb_cti_nxt[1] = 1'b1                  ;
                wb_cti_nxt[0] = wb_ack && wb_stb_o || wb_cti_o[0];
           wb_cti_nxt[0] = wb_ack & wb_stb_o | wb_cti_o[0];
                if ((wb_err_i || wb_rty_i || wb_ack && wb_cti_o == 3'b111) && wb_stb_o)
           if ((wb_err_i | wb_rty_i | wb_ack & wb_cti_o == 3'b111) & wb_stb_o)
                        wb_fsm_state_nxt = wb_fsm_idle;
                        wb_fsm_state_nxt = wb_fsm_idle;
                else
                else
                        wb_fsm_state_nxt = wb_fsm_last;
                        wb_fsm_state_nxt = wb_fsm_last;
        end
        end
        // default state
        // default state
Line 314... Line 277...
//
//
// WB FSM - output signals
// WB FSM - output signals
// 
// 
always @(posedge wb_clk_i or posedge wb_rst_i) begin
always @(posedge wb_clk_i or posedge wb_rst_i) begin
        if (wb_rst_i) begin
        if (wb_rst_i) begin
                wb_cyc_o        <= #1 1'b0;
         wb_cyc_o       <=  1'b0;
                wb_stb_o        <= #1 1'b0;
         wb_stb_o       <=  1'b0;
                wb_cti_o        <= #1 3'b111;
         wb_cti_o       <=  3'b111;
                wb_bte_o        <= #1 2'b01;    // 4-beat wrap burst = constant
         wb_bte_o       <=  2'b01;      // 4-beat wrap burst = constant
`ifdef OR1200_WB_CAB
`ifdef OR1200_WB_CAB
                wb_cab_o        <= #1 1'b0;
         wb_cab_o       <=  1'b0;
 
`endif
 
         wb_we_o                <=  1'b0;
 
         wb_sel_o       <=  4'hf;
 
         wb_adr_o       <=  {aw{1'b0}};
 
`ifdef OR1200_NO_DC
 
         wb_dat_o       <=  {dw{1'b0}};
`endif
`endif
                wb_we_o         <= #1 1'b0;
 
                wb_sel_o        <= #1 4'hf;
 
                wb_adr_o        <= #1 {aw{1'b0}};
 
                wb_dat_o        <= #1 {dw{1'b0}};
 
        end
        end
        else begin
        else begin
                wb_cyc_o        <= #1 wb_cyc_nxt;
         wb_cyc_o       <=  wb_cyc_nxt;
//              wb_stb_o        <= #1 wb_stb_nxt;
         //             wb_stb_o        <=  wb_stb_nxt;
                if (wb_ack && wb_cti_o == 3'b111)
         if (wb_ack & wb_cti_o == 3'b111)
                        wb_stb_o        <= #1 1'b0;
           wb_stb_o        <=  1'b0;
                else
                else
                        wb_stb_o        <= #1 wb_stb_nxt;
           wb_stb_o        <=  wb_stb_nxt;
                wb_cti_o        <= #1 wb_cti_nxt;
         wb_cti_o       <=  wb_cti_nxt;
                wb_bte_o        <= #1 2'b01;    // 4-beat wrap burst = constant
         wb_bte_o       <=  2'b01;      // 4-beat wrap burst = constant
`ifdef OR1200_WB_CAB
`ifdef OR1200_WB_CAB
                wb_cab_o        <= #1 biu_cab_i;
         wb_cab_o       <=  biu_cab_i;
`endif
`endif
                // we and sel - set at beginning of access 
                // we and sel - set at beginning of access 
                if (wb_fsm_state_cur == wb_fsm_idle) begin
                if (wb_fsm_state_cur == wb_fsm_idle) begin
                        wb_we_o         <= #1 biu_we_i;
            wb_we_o             <=  biu_we_i;
                        wb_sel_o        <= #1 biu_sel_i;
            wb_sel_o    <=  biu_sel_i;
                end
                end
                // adr - set at beginning of access and changed at every termination 
                // adr - set at beginning of access and changed at every termination 
                if (wb_fsm_state_cur == wb_fsm_idle) begin
                if (wb_fsm_state_cur == wb_fsm_idle) begin
                   wb_adr_o     <= #1 biu_adr_i;
            wb_adr_o    <=  biu_adr_i;
                end
                end
                else if (wb_stb_o && wb_ack) begin
         else if (wb_stb_o & wb_ack) begin
                        wb_adr_o[3:2]   <= #1 wb_adr_o[3:2] + 1'b1;
            wb_adr_o[3:2]       <=  wb_adr_o[3:2] + 1'b1;
                end
                end
 
`ifdef OR1200_NO_DC
                // dat - write data changed after avery subsequent write access
                // dat - write data changed after avery subsequent write access
                if (!wb_stb_o) begin
                if (!wb_stb_o) begin
                        wb_dat_o        <= #1 biu_dat_i;
            wb_dat_o    <=  biu_dat_i;
                end
                end
 
`endif
        end
        end
end
end
 
 
//
//
// WB & BIU termination toggle counters
// WB & BIU termination toggle counters
// 
// 
always @(posedge wb_clk_i or posedge wb_rst_i) begin
always @(posedge wb_clk_i or posedge wb_rst_i) begin
        if (wb_rst_i) begin
        if (wb_rst_i) begin
                wb_ack_cnt      <= #1 1'b0;
         wb_ack_cnt     <=  1'b0;
                wb_err_cnt      <= #1 1'b0;
         wb_err_cnt     <=  1'b0;
                wb_rty_cnt      <= #1 1'b0;
         wb_rty_cnt     <=  1'b0;
        end
        end
        else begin
        else begin
                // WB ack toggle counter
                // WB ack toggle counter
                if (wb_fsm_state_cur == wb_fsm_idle || !clmode)
         if (wb_fsm_state_cur == wb_fsm_idle | !clmode)
                        wb_ack_cnt      <= #1 1'b0;
           wb_ack_cnt   <=  1'b0;
                else if (wb_stb_o && wb_ack)
         else if (wb_stb_o & wb_ack)
                        wb_ack_cnt      <= #1 !wb_ack_cnt;
           wb_ack_cnt   <=  !wb_ack_cnt;
                // WB err toggle counter
                // WB err toggle counter
                if (wb_fsm_state_cur == wb_fsm_idle || !clmode)
         if (wb_fsm_state_cur == wb_fsm_idle | !clmode)
                        wb_err_cnt      <= #1 1'b0;
           wb_err_cnt   <=  1'b0;
                else if (wb_stb_o && wb_err_i)
         else if (wb_stb_o & wb_err_i)
                        wb_err_cnt      <= #1 !wb_err_cnt;
           wb_err_cnt   <=  !wb_err_cnt;
                // WB rty toggle counter
                // WB rty toggle counter
                if (wb_fsm_state_cur == wb_fsm_idle || !clmode)
         if (wb_fsm_state_cur == wb_fsm_idle | !clmode)
                        wb_rty_cnt      <= #1 1'b0;
           wb_rty_cnt   <=  1'b0;
                else if (wb_stb_o && wb_rty_i)
         else if (wb_stb_o & wb_rty_i)
                        wb_rty_cnt      <= #1 !wb_rty_cnt;
           wb_rty_cnt   <=  !wb_rty_cnt;
        end
        end
end
end
 
 
always @(posedge clk or posedge rst) begin
always @(posedge clk or posedge rst) begin
        if (rst) begin
        if (rst) begin
                biu_stb_reg     <= #1 1'b0;
         biu_stb_reg    <=  1'b0;
                biu_ack_cnt     <= #1 1'b0;
         biu_ack_cnt    <=  1'b0;
                biu_err_cnt     <= #1 1'b0;
         biu_err_cnt    <=  1'b0;
                biu_rty_cnt     <= #1 1'b0;
         biu_rty_cnt    <=  1'b0;
`ifdef OR1200_WB_RETRY
`ifdef OR1200_WB_RETRY
                retry_cnt       <= {`OR1200_WB_RETRY{1'b0}};
                retry_cnt       <= {`OR1200_WB_RETRY{1'b0}};
`endif
`endif
        end
        end
        else begin
        else begin
                // BIU strobe
                // BIU strobe
                if (biu_stb_i && !biu_cab_i && biu_ack_o)
         if (biu_stb_i & !biu_cab_i & biu_ack_o)
                        biu_stb_reg     <= #1 1'b0;
           biu_stb_reg  <=  1'b0;
                else
                else
                        biu_stb_reg     <= #1 biu_stb_i;
           biu_stb_reg  <=  biu_stb_i;
                // BIU ack toggle counter
                // BIU ack toggle counter
                if (wb_fsm_state_cur == wb_fsm_idle || !clmode)
         if (wb_fsm_state_cur == wb_fsm_idle | !clmode)
                        biu_ack_cnt     <= #1 1'b0 ;
           biu_ack_cnt  <=  1'b0 ;
                else if (biu_ack_o)
                else if (biu_ack_o)
                        biu_ack_cnt     <= #1 !biu_ack_cnt ;
           biu_ack_cnt  <=  !biu_ack_cnt ;
                // BIU err toggle counter
                // BIU err toggle counter
                if (wb_fsm_state_cur == wb_fsm_idle || !clmode)
         if (wb_fsm_state_cur == wb_fsm_idle | !clmode)
                        biu_err_cnt     <= #1 1'b0 ;
           biu_err_cnt  <=  1'b0 ;
                else if (wb_err_i && biu_err_o)
         else if (wb_err_i & biu_err_o)
                        biu_err_cnt     <= #1 !biu_err_cnt ;
           biu_err_cnt  <=  !biu_err_cnt ;
                // BIU rty toggle counter
                // BIU rty toggle counter
                if (wb_fsm_state_cur == wb_fsm_idle || !clmode)
         if (wb_fsm_state_cur == wb_fsm_idle | !clmode)
                        biu_rty_cnt     <= #1 1'b0 ;
           biu_rty_cnt  <=  1'b0 ;
                else if (biu_rty)
                else if (biu_rty)
                        biu_rty_cnt     <= #1 !biu_rty_cnt ;
           biu_rty_cnt  <=  !biu_rty_cnt ;
`ifdef OR1200_WB_RETRY
`ifdef OR1200_WB_RETRY
                if (biu_ack_o || biu_err_o)
         if (biu_ack_o | biu_err_o)
                        retry_cnt       <= #1 {`OR1200_WB_RETRY{1'b0}};
           retry_cnt    <=  {`OR1200_WB_RETRY{1'b0}};
                else if (biu_rty)
                else if (biu_rty)
                        retry_cnt       <= #1 retry_cnt + 1'b1;
           retry_cnt    <=  retry_cnt + 1'b1;
`endif
`endif
        end
        end
end
end
 
 
assign biu_stb = biu_stb_i && biu_stb_reg;
   assign biu_stb = biu_stb_i & biu_stb_reg;
 
 
//
//
// Input BIU data bus
// Input BIU data bus
//
//
assign  biu_dat_o       = wb_dat_i;
assign  biu_dat_o       = wb_dat_i;
 
 
//
//
// Input BIU termination signals 
// Input BIU termination signals 
//
//
assign  biu_rty         = (wb_fsm_state_cur == wb_fsm_trans) && wb_rty_i && wb_stb_o && (wb_rty_cnt ~^ biu_rty_cnt);
   assign       biu_rty         = (wb_fsm_state_cur == wb_fsm_trans) & wb_rty_i & wb_stb_o & (wb_rty_cnt ~^ biu_rty_cnt);
assign  biu_ack_o       = (wb_fsm_state_cur == wb_fsm_trans) && wb_ack && wb_stb_o && (wb_ack_cnt ~^ biu_ack_cnt);
   assign       biu_ack_o       = (wb_fsm_state_cur == wb_fsm_trans) & wb_ack & wb_stb_o & (wb_ack_cnt ~^ biu_ack_cnt);
assign  biu_err_o       = (wb_fsm_state_cur == wb_fsm_trans) && wb_err_i && wb_stb_o && (wb_err_cnt ~^ biu_err_cnt)
   assign       biu_err_o       = (wb_fsm_state_cur == wb_fsm_trans) & wb_err_i & wb_stb_o & (wb_err_cnt ~^ biu_err_cnt)
`ifdef OR1200_WB_RETRY
`ifdef OR1200_WB_RETRY
                        || biu_rty && retry_cnt[`OR1200_WB_RETRY-1];
     | biu_rty & retry_cnt[`OR1200_WB_RETRY-1];
`else
`else
                        ;
                        ;
`endif
`endif
 
 
 
 

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