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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_wb_biu.v] - Diff between revs 10 and 142

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////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: or1200_wb_biu.v,v $
 
// Revision 2.0  2010/06/30 11:00:00  ORSoC
 
// Major update: 
 
// Structure reordered and bugs fixed. 
 
//
 
// Revision 1.7  2004/04/05 08:29:57  lampret
 
// Merged branch_qmem into main tree.
 
//
// Revision 1.6.4.1  2003/07/08 15:36:37  lampret
// Revision 1.6.4.1  2003/07/08 15:36:37  lampret
// Added embedded memory QMEM.
// Added embedded memory QMEM.
//
//
// Revision 1.6  2003/04/07 20:57:46  lampret
// Revision 1.6  2003/04/07 20:57:46  lampret
// Fixed OR1200_CLKDIV_x_SUPPORTED defines. Fixed order of ifdefs.
// Fixed OR1200_CLKDIV_x_SUPPORTED defines. Fixed order of ifdefs.
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output                  biu_err_o;      // err output
output                  biu_err_o;      // err output
 
 
//
//
// Registers
// Registers
//
//
reg     [1:0]            valid_div;      // Used for synchronization
wire                            wb_ack;         // normal termination
`ifdef OR1200_REGISTERED_OUTPUTS
 
reg     [aw-1:0] wb_adr_o;       // address bus outputs
reg     [aw-1:0] wb_adr_o;       // address bus outputs
reg                     wb_cyc_o;       // cycle output
reg                     wb_cyc_o;       // cycle output
reg                     wb_stb_o;       // strobe output
reg                     wb_stb_o;       // strobe output
reg                     wb_we_o;        // indicates write transfer
reg                     wb_we_o;        // indicates write transfer
reg     [3:0]            wb_sel_o;       // byte select outputs
reg     [3:0]            wb_sel_o;       // byte select outputs
`ifdef OR1200_WB_CAB
`ifdef OR1200_WB_CAB
reg                     wb_cab_o;       // CAB output
reg                     wb_cab_o;       // CAB output
`endif
`endif
`ifdef OR1200_WB_B3
`ifdef OR1200_WB_B3
reg     [1:0]            burst_len;      // burst counter
 
reg     [2:0]            wb_cti_o;       // cycle type identifier
reg     [2:0]            wb_cti_o;       // cycle type identifier
 
reg     [1:0]                    wb_bte_o;       // burst type extension
`endif
`endif
reg     [dw-1:0] wb_dat_o;       // output data bus
reg     [dw-1:0] wb_dat_o;       // output data bus
`endif
 
`ifdef OR1200_REGISTERED_INPUTS
 
reg                     long_ack_o;     // normal termination
 
reg                     long_err_o;     // error termination
 
reg     [dw-1:0] biu_dat_o;      // output data bus
 
`else
 
wire                    long_ack_o;     // normal termination
 
wire                    long_err_o;     // error termination
 
`endif
 
wire                    aborted;        // Graceful abort
 
reg                     aborted_r;      // Graceful abort
 
wire                    retry;          // Retry
 
`ifdef OR1200_WB_RETRY
 
reg     [`OR1200_WB_RETRY-1:0] retry_cntr;       // Retry counter
 
`endif
 
 
 
//
`ifdef OR1200_WB_RETRY
// WISHBONE I/F <-> Internal RISC I/F conversion
reg     [`OR1200_WB_RETRY-1:0]   retry_cnt;      // Retry counter
//
 
 
 
//
 
// Address bus
 
//
 
`ifdef OR1200_REGISTERED_OUTPUTS
 
always @(posedge wb_clk_i or posedge wb_rst_i)
 
        if (wb_rst_i)
 
                wb_adr_o <= #1 {aw{1'b0}};
 
        else if ((biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~aborted & ~(wb_stb_o & ~wb_ack_i))
 
                wb_adr_o <= #1 biu_adr_i;
 
`else
`else
assign wb_adr_o = biu_adr_i;
wire                            retry_cnt       = 1'b0;
`endif
`endif
 
`ifdef OR1200_WB_B3
//
reg     [1:0]                    burst_len;      // burst counter
// Input data bus
 
//
 
`ifdef OR1200_REGISTERED_INPUTS
 
always @(posedge wb_clk_i or posedge wb_rst_i)
 
        if (wb_rst_i)
 
                biu_dat_o <= #1 32'h0000_0000;
 
        else if (wb_ack_i)
 
                biu_dat_o <= #1 wb_dat_i;
 
`else
 
assign biu_dat_o = wb_dat_i;
 
`endif
`endif
 
 
//
reg                             biu_stb_reg;    // WB strobe
// Output data bus
wire                            biu_stb;        // WB strobe
//
reg                             wb_cyc_nxt;     // next WB cycle value
`ifdef OR1200_REGISTERED_OUTPUTS
reg                             wb_stb_nxt;     // next WB strobe value
always @(posedge wb_clk_i or posedge wb_rst_i)
reg     [2:0]                    wb_cti_nxt;     // next cycle type identifier value
        if (wb_rst_i)
 
                wb_dat_o <= #1 {dw{1'b0}};
reg                             wb_ack_cnt;     // WB ack toggle counter
        else if ((biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~aborted)
reg                             wb_err_cnt;     // WB err toggle counter
                wb_dat_o <= #1 biu_dat_i;
reg                             wb_rty_cnt;     // WB rty toggle counter
`else
reg                             biu_ack_cnt;    // BIU ack toggle counter
assign wb_dat_o = biu_dat_i;
reg                             biu_err_cnt;    // BIU err toggle counter
`endif
reg                             biu_rty_cnt;    // BIU rty toggle counter
 
wire                            biu_rty;        // BIU rty indicator
 
 
 
reg     [1:0]                    wb_fsm_state_cur;       // WB FSM - surrent state
 
reg     [1:0]                    wb_fsm_state_nxt;       // WB FSM - next state
 
wire    [1:0]                    wb_fsm_idle     = 2'h0; // WB FSM state - IDLE
 
wire    [1:0]                    wb_fsm_trans    = 2'h1; // WB FSM state - normal TRANSFER
 
wire    [1:0]                    wb_fsm_last     = 2'h2; // EB FSM state - LAST transfer
 
 
//
//
// Valid_div counts RISC clock cycles by modulo 4
// WISHBONE I/F <-> Internal RISC I/F conversion
// and is used to synchronize external WB i/f to
 
// RISC clock
 
//
 
always @(posedge clk or posedge rst)
 
        if (rst)
 
                valid_div <= #1 2'b0;
 
        else
 
                valid_div <= #1 valid_div + 1'd1;
 
 
 
//
//
// biu_ack_o is one RISC clock cycle long long_ack_o.
//assign wb_ack = wb_ack_i;
// long_ack_o is one, two or four RISC clock cycles long because
assign wb_ack = wb_ack_i && !wb_err_i && !wb_rty_i;
// WISHBONE can work at 1, 1/2 or 1/4 RISC clock.
 
//
 
assign biu_ack_o = long_ack_o
 
`ifdef OR1200_CLKDIV_2_SUPPORTED
 
                & (valid_div[0] | ~clmode[0])
 
`ifdef OR1200_CLKDIV_4_SUPPORTED
 
                & (valid_div[1] | ~clmode[1])
 
`endif
 
`endif
 
                ;
 
 
 
//
//
// Acknowledgment of the data to the RISC
// WB FSM - register part
//
//
// long_ack_o
always @(posedge wb_clk_i or posedge wb_rst_i) begin
//
 
`ifdef OR1200_REGISTERED_INPUTS
 
always @(posedge wb_clk_i or posedge wb_rst_i)
 
        if (wb_rst_i)
        if (wb_rst_i)
                long_ack_o <= #1 1'b0;
                wb_fsm_state_cur <= #1 wb_fsm_idle;
        else
        else
                long_ack_o <= #1 wb_ack_i & ~aborted;
                wb_fsm_state_cur <= #1 wb_fsm_state_nxt;
`else
end
assign long_ack_o = wb_ack_i & ~aborted_r;
 
`endif
 
 
 
//
//
// biu_err_o is one RISC clock cycle long long_err_o.
// WB burst tength counter
// long_err_o is one, two or four RISC clock cycles long because
 
// WISHBONE can work at 1, 1/2 or 1/4 RISC clock.
 
//
//
assign biu_err_o = long_err_o
always @(posedge wb_clk_i or posedge wb_rst_i) begin
`ifdef OR1200_CLKDIV_2_SUPPORTED
        if (wb_rst_i) begin
                & (valid_div[0] | ~clmode[0])
                burst_len <= #1 2'h0;
`ifdef OR1200_CLKDIV_4_SUPPORTED
        end
                & (valid_div[1] | ~clmode[1])
        else begin
`endif
                // burst counter
`endif
                if (wb_fsm_state_cur == wb_fsm_idle)
                ;
                        burst_len <= #1 2'h2;
 
                else if (wb_stb_o && wb_ack)
 
                        burst_len <= #1 burst_len - 1'b1;
 
        end
 
end
 
 
//
//
// Error termination
// WB FSM - combinatorial part
//
 
// long_err_o
 
//
//
`ifdef OR1200_REGISTERED_INPUTS
always @(wb_fsm_state_cur or burst_len or
always @(posedge wb_clk_i or posedge wb_rst_i)
         wb_err_i or wb_rty_i or wb_ack or wb_cti_o or wb_sel_o or wb_stb_o or wb_we_o or
        if (wb_rst_i)
         biu_cyc_i or biu_stb or biu_cab_i or biu_sel_i or biu_we_i) begin
                long_err_o <= #1 1'b0;
// States of WISHBONE Finite State Machine
 
        case(wb_fsm_state_cur)
 
        // IDLE 
 
        wb_fsm_idle : begin
 
                wb_cyc_nxt = biu_cyc_i && biu_stb;
 
                wb_stb_nxt = biu_cyc_i && biu_stb;
 
                wb_cti_nxt = {!biu_cab_i, 1'b1, !biu_cab_i};
 
                if (biu_cyc_i && biu_stb)
 
                        wb_fsm_state_nxt = wb_fsm_trans;
        else
        else
                long_err_o <= #1 wb_err_i & ~aborted;
                        wb_fsm_state_nxt = wb_fsm_idle;
`else
        end
assign long_err_o = wb_err_i & ~aborted_r;
        // normal TRANSFER
`endif
        wb_fsm_trans : begin
 
                wb_cyc_nxt = !wb_stb_o || !wb_err_i && !wb_rty_i && !(wb_ack && wb_cti_o == 3'b111);
//
                wb_stb_nxt = !wb_stb_o || !wb_err_i && !wb_rty_i && !wb_ack || !wb_err_i && !wb_rty_i && wb_cti_o == 3'b010 && !wb_we_o;
// Retry counter
                wb_cti_nxt[2] = wb_stb_o && wb_ack && burst_len == 'h0 || wb_cti_o[2];
//
                wb_cti_nxt[1] = 1'b1  ;
// Assert 'retry' when 'wb_rty_i' is sampled high and keep it high
                wb_cti_nxt[0] = wb_stb_o && wb_ack && burst_len == 'h0 || wb_cti_o[0];
// until retry counter doesn't expire
                //if ((!biu_cyc_i || !biu_stb || !biu_cab_i) && wb_cti_o == 3'b010  || biu_sel_i != wb_sel_o || biu_we_i != wb_we_o)
// 
                if ((!biu_cyc_i || !biu_stb || !biu_cab_i || biu_sel_i != wb_sel_o || biu_we_i != wb_we_o) && wb_cti_o == 3'b010)
`ifdef OR1200_WB_RETRY
                        wb_fsm_state_nxt = wb_fsm_last;
assign retry = wb_rty_i | (|retry_cntr);
                else if ((wb_err_i || wb_rty_i || wb_ack && wb_cti_o == 3'b111) && wb_stb_o)
`else
                        wb_fsm_state_nxt = wb_fsm_idle;
assign retry = 1'b0;
 
`endif
 
`ifdef OR1200_WB_RETRY
 
always @(posedge wb_clk_i or posedge wb_rst_i)
 
        if (wb_rst_i)
 
                retry_cntr <= #1 1'b0;
 
        else if (wb_rty_i)
 
                retry_cntr <= #1 {`OR1200_WB_RETRY{1'b1}};
 
        else if (retry_cntr)
 
                retry_cntr <= #1 retry_cntr - 7'd1;
 
`endif
 
 
 
//
 
// Graceful completion of aborted transfers
 
//
 
// Assert 'aborted' when 1) current transfer is in progress (wb_stb_o; which
 
// we know is only asserted together with wb_cyc_o) 2) and in next WB clock cycle
 
// wb_stb_o would be deasserted (biu_cyc_i and biu_stb_i are low) 3) and
 
// there is no termination of current transfer in this WB clock cycle (wb_ack_i
 
// and wb_err_i are low).
 
// 'aborted_r' is registered 'aborted' and extended until this "aborted" transfer
 
// is properly terminated with wb_ack_i/wb_err_i.
 
// 
 
assign aborted = wb_stb_o & ~(biu_cyc_i & biu_stb_i) & ~(wb_ack_i | wb_err_i);
 
always @(posedge wb_clk_i or posedge wb_rst_i)
 
        if (wb_rst_i)
 
                aborted_r <= #1 1'b0;
 
        else if (wb_ack_i | wb_err_i)
 
                aborted_r <= #1 1'b0;
 
        else if (aborted)
 
                aborted_r <= #1 1'b1;
 
 
 
//
 
// WB cyc_o
 
//
 
// Either 1) normal transfer initiated by biu_cyc_i (and biu_cab_i if
 
// bursts are enabled) and possibly suspended by 'retry'
 
// or 2) extended "aborted" transfer
 
//
 
`ifdef OR1200_REGISTERED_OUTPUTS
 
always @(posedge wb_clk_i or posedge wb_rst_i)
 
        if (wb_rst_i)
 
                wb_cyc_o <= #1 1'b0;
 
        else
        else
`ifdef OR1200_NO_BURSTS
                        wb_fsm_state_nxt = wb_fsm_trans;
                wb_cyc_o <= #1 biu_cyc_i & ~wb_ack_i & ~retry | aborted & ~wb_ack_i;
        end
`else
        // LAST transfer
                wb_cyc_o <= #1 biu_cyc_i & ~wb_ack_i & ~retry | biu_cab_i | aborted & ~wb_ack_i;
        wb_fsm_last : begin
`endif
                wb_cyc_nxt = !wb_stb_o || !wb_err_i && !wb_rty_i && !(wb_ack && wb_cti_o == 3'b111);
`else
                wb_stb_nxt = !wb_stb_o || !wb_err_i && !wb_rty_i && !(wb_ack && wb_cti_o == 3'b111);
`ifdef OR1200_NO_BURSTS
                wb_cti_nxt[2] = wb_ack && wb_stb_o || wb_cti_o[2];
assign wb_cyc_o = biu_cyc_i & ~retry;
                wb_cti_nxt[1] = 1'b1                  ;
`else
                wb_cti_nxt[0] = wb_ack && wb_stb_o || wb_cti_o[0];
assign wb_cyc_o = biu_cyc_i | biu_cab_i & ~retry;
                if ((wb_err_i || wb_rty_i || wb_ack && wb_cti_o == 3'b111) && wb_stb_o)
`endif
                        wb_fsm_state_nxt = wb_fsm_idle;
`endif
                else
 
                        wb_fsm_state_nxt = wb_fsm_last;
 
        end
 
        // default state
 
        default:begin
 
                wb_cyc_nxt = 1'bx;
 
                wb_stb_nxt = 1'bx;
 
                wb_cti_nxt = 3'bxxx;
 
                wb_fsm_state_nxt = 2'bxx;
 
        end
 
        endcase
 
end
 
 
//
//
// WB stb_o
// WB FSM - output signals
//
//
`ifdef OR1200_REGISTERED_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i) begin
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i) begin
        if (wb_rst_i)
                wb_cyc_o        <= #1 1'b0;
                wb_stb_o <= #1 1'b0;
                wb_stb_o <= #1 1'b0;
        else
                wb_cti_o        <= #1 3'b111;
                wb_stb_o <= #1 (biu_cyc_i & biu_stb_i) & ~wb_ack_i & ~retry | aborted & ~wb_ack_i;
                wb_bte_o        <= #1 2'b01;    // 4-beat wrap burst = constant
`else
`ifdef OR1200_WB_CAB
assign wb_stb_o = biu_cyc_i & biu_stb_i;
                wb_cab_o        <= #1 1'b0;
`endif
`endif
 
 
//
 
// WB we_o
 
//
 
`ifdef OR1200_REGISTERED_OUTPUTS
 
always @(posedge wb_clk_i or posedge wb_rst_i)
 
        if (wb_rst_i)
 
                wb_we_o <= #1 1'b0;
                wb_we_o <= #1 1'b0;
 
                wb_sel_o        <= #1 4'hf;
 
                wb_adr_o        <= #1 {aw{1'b0}};
 
                wb_dat_o        <= #1 {dw{1'b0}};
 
        end
 
        else begin
 
                wb_cyc_o        <= #1 wb_cyc_nxt;
 
//              wb_stb_o        <= #1 wb_stb_nxt;
 
                if (wb_ack && wb_cti_o == 3'b111)
 
                        wb_stb_o        <= #1 1'b0;
        else
        else
                wb_we_o <= #1 biu_cyc_i & biu_stb_i & biu_we_i | aborted & wb_we_o;
                        wb_stb_o        <= #1 wb_stb_nxt;
`else
                wb_cti_o        <= #1 wb_cti_nxt;
assign wb_we_o = biu_cyc_i & biu_stb_i & biu_we_i;
                wb_bte_o        <= #1 2'b01;    // 4-beat wrap burst = constant
 
`ifdef OR1200_WB_CAB
 
                wb_cab_o        <= #1 biu_cab_i;
`endif
`endif
 
                // we and sel - set at beginning of access 
//
                if (wb_fsm_state_cur == wb_fsm_idle) begin
// WB sel_o
                        wb_we_o         <= #1 biu_we_i;
//
 
`ifdef OR1200_REGISTERED_OUTPUTS
 
always @(posedge wb_clk_i or posedge wb_rst_i)
 
        if (wb_rst_i)
 
                wb_sel_o <= #1 4'b0000;
 
        else
 
                wb_sel_o <= #1 biu_sel_i;
                wb_sel_o <= #1 biu_sel_i;
`else
                end
assign wb_sel_o = biu_sel_i;
                // adr - set at beginning of access and changed at every termination 
 
                if (wb_fsm_state_cur == wb_fsm_idle) begin
 
                   wb_adr_o     <= #1 biu_adr_i;
 
                end
 
                else if (wb_stb_o && wb_ack) begin
 
                        wb_adr_o[3:2]   <= #1 wb_adr_o[3:2] + 1'b1;
 
                end
 
                // dat - write data changed after avery subsequent write access
 
                if (!wb_stb_o) begin
 
                        wb_dat_o        <= #1 biu_dat_i;
 
                end
 
        end
 
end
 
 
 
//
 
// WB & BIU termination toggle counters
 
// 
 
always @(posedge wb_clk_i or posedge wb_rst_i) begin
 
        if (wb_rst_i) begin
 
                wb_ack_cnt      <= #1 1'b0;
 
                wb_err_cnt      <= #1 1'b0;
 
                wb_rty_cnt      <= #1 1'b0;
 
        end
 
        else begin
 
                // WB ack toggle counter
 
                if (wb_fsm_state_cur == wb_fsm_idle || !clmode)
 
                        wb_ack_cnt      <= #1 1'b0;
 
                else if (wb_stb_o && wb_ack)
 
                        wb_ack_cnt      <= #1 !wb_ack_cnt;
 
                // WB err toggle counter
 
                if (wb_fsm_state_cur == wb_fsm_idle || !clmode)
 
                        wb_err_cnt      <= #1 1'b0;
 
                else if (wb_stb_o && wb_err_i)
 
                        wb_err_cnt      <= #1 !wb_err_cnt;
 
                // WB rty toggle counter
 
                if (wb_fsm_state_cur == wb_fsm_idle || !clmode)
 
                        wb_rty_cnt      <= #1 1'b0;
 
                else if (wb_stb_o && wb_rty_i)
 
                        wb_rty_cnt      <= #1 !wb_rty_cnt;
 
        end
 
end
 
 
 
always @(posedge clk or posedge rst) begin
 
        if (rst) begin
 
                biu_stb_reg     <= #1 1'b0;
 
                biu_ack_cnt     <= #1 1'b0;
 
                biu_err_cnt     <= #1 1'b0;
 
                biu_rty_cnt     <= #1 1'b0;
 
`ifdef OR1200_WB_RETRY
 
                retry_cnt       <= {`OR1200_WB_RETRY{1'b0}};
`endif
`endif
 
        end
`ifdef OR1200_WB_CAB
        else begin
//
                // BIU strobe
// WB cab_o
                if (biu_stb_i && !biu_cab_i && biu_ack_o)
//
                        biu_stb_reg     <= #1 1'b0;
`ifdef OR1200_REGISTERED_OUTPUTS
 
always @(posedge wb_clk_i or posedge wb_rst_i)
 
        if (wb_rst_i)
 
                wb_cab_o <= #1 1'b0;
 
        else
        else
                wb_cab_o <= #1 biu_cab_i;
                        biu_stb_reg     <= #1 biu_stb_i;
`else
                // BIU ack toggle counter
assign wb_cab_o = biu_cab_i;
                if (wb_fsm_state_cur == wb_fsm_idle || !clmode)
`endif
                        biu_ack_cnt     <= #1 1'b0 ;
 
                else if (biu_ack_o)
 
                        biu_ack_cnt     <= #1 !biu_ack_cnt ;
 
                // BIU err toggle counter
 
                if (wb_fsm_state_cur == wb_fsm_idle || !clmode)
 
                        biu_err_cnt     <= #1 1'b0 ;
 
                else if (wb_err_i && biu_err_o)
 
                        biu_err_cnt     <= #1 !biu_err_cnt ;
 
                // BIU rty toggle counter
 
                if (wb_fsm_state_cur == wb_fsm_idle || !clmode)
 
                        biu_rty_cnt     <= #1 1'b0 ;
 
                else if (biu_rty)
 
                        biu_rty_cnt     <= #1 !biu_rty_cnt ;
 
`ifdef OR1200_WB_RETRY
 
                if (biu_ack_o || biu_err_o)
 
                        retry_cnt       <= #1 {`OR1200_WB_RETRY{1'b0}};
 
                else if (biu_rty)
 
                        retry_cnt       <= #1 retry_cnt + 1'b1;
`endif
`endif
 
        end
 
end
 
 
 
assign biu_stb = biu_stb_i && biu_stb_reg;
 
 
`ifdef OR1200_WB_B3
 
//
//
// Count burst beats
// Input BIU data bus
//
//
always @(posedge wb_clk_i or posedge wb_rst_i)
assign  biu_dat_o       = wb_dat_i;
        if (wb_rst_i)
 
                burst_len <= #1 2'b00;
 
        else if (biu_cab_i && burst_len && wb_ack_i)
 
                burst_len <= #1 burst_len - 1'b1;
 
        else if (~biu_cab_i)
 
                burst_len <= #1 2'b11;
 
 
 
//
//
// WB cti_o
// Input BIU termination signals 
//
//
`ifdef OR1200_REGISTERED_OUTPUTS
assign  biu_rty         = (wb_fsm_state_cur == wb_fsm_trans) && wb_rty_i && wb_stb_o && (wb_rty_cnt ~^ biu_rty_cnt);
always @(posedge wb_clk_i or posedge wb_rst_i)
assign  biu_ack_o       = (wb_fsm_state_cur == wb_fsm_trans) && wb_ack && wb_stb_o && (wb_ack_cnt ~^ biu_ack_cnt);
        if (wb_rst_i)
assign  biu_err_o       = (wb_fsm_state_cur == wb_fsm_trans) && wb_err_i && wb_stb_o && (wb_err_cnt ~^ biu_err_cnt)
                wb_cti_o <= #1 3'b000;  // classic cycle
`ifdef OR1200_WB_RETRY
`ifdef OR1200_NO_BURSTS
                        || biu_rty && retry_cnt[`OR1200_WB_RETRY-1];
        else
 
                wb_cti_o <= #1 3'b111;  // end-of-burst
 
`else
 
        else if (biu_cab_i && burst_len[1])
 
                wb_cti_o <= #1 3'b010;  // incrementing burst cycle
 
        else if (biu_cab_i && wb_ack_i)
 
                wb_cti_o <= #1 3'b111;  // end-of-burst
 
`endif  // OR1200_NO_BURSTS
 
`else
`else
Unsupported !!!;
                        ;
`endif
`endif
 
 
//
 
// WB bte_o
 
//
 
assign wb_bte_o = 2'b01;        // 4-beat wrap burst
 
 
 
`endif  // OR1200_WB_B3
 
 
 
endmodule
endmodule
 
 
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