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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's Write-back Mux ////
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//// OR1200's Write-back Mux ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// http://www.opencores.org/project,or1k ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// CPU's write-back stage of the pipeline ////
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//// CPU's write-back stage of the pipeline ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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//
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//
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// $Log: or1200_wbmux.v,v $
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// $Log: or1200_wbmux.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// No update
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// No update
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//
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// Revision 1.3 2004/06/08 18:17:36 lampret
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// Non-functional changes. Coding style fixes.
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//
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// Revision 1.2 2002/03/29 15:16:56 lampret
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// Some of the warnings fixed.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.8 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.7 2001/10/14 13:12:10 lampret
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// MP3 version.
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//
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// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
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// no message
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//
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// Revision 1.2 2001/08/09 13:39:33 lampret
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// Major clean-up.
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//
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// Revision 1.1 2001/07/20 00:46:23 lampret
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// Development version of RTL. Libraries are missing.
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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// Clock and reset
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// Clock and reset
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clk, rst,
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clk, rst,
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// Internal i/f
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// Internal i/f
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wb_freeze, rfwb_op,
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wb_freeze, rfwb_op,
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muxin_a, muxin_b, muxin_c, muxin_d,
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muxin_a, muxin_b, muxin_c, muxin_d, muxin_e,
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muxout, muxreg, muxreg_valid
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muxout, muxreg, muxreg_valid
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);
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);
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parameter width = `OR1200_OPERAND_WIDTH;
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parameter width = `OR1200_OPERAND_WIDTH;
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input [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op;
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input [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op;
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input [width-1:0] muxin_a;
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input [width-1:0] muxin_a;
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input [width-1:0] muxin_b;
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input [width-1:0] muxin_b;
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input [width-1:0] muxin_c;
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input [width-1:0] muxin_c;
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input [width-1:0] muxin_d;
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input [width-1:0] muxin_d;
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input [width-1:0] muxin_e;
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output [width-1:0] muxout;
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output [width-1:0] muxout;
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output [width-1:0] muxreg;
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output [width-1:0] muxreg;
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output muxreg_valid;
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output muxreg_valid;
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//
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//
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end
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end
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//
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//
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// Write-back multiplexer
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// Write-back multiplexer
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//
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//
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always @(muxin_a or muxin_b or muxin_c or muxin_d or rfwb_op) begin
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always @(muxin_a or muxin_b or muxin_c or muxin_d or muxin_e or rfwb_op) begin
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`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
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`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
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case(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case infer_mux
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case(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case infer_mux
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`else
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`else
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case(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case
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case(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case
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`endif
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`endif
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2'b00: muxout = muxin_a;
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`OR1200_RFWBOP_ALU: muxout = muxin_a;
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2'b01: begin
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`OR1200_RFWBOP_LSU: begin
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muxout = muxin_b;
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muxout = muxin_b;
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`ifdef OR1200_VERBOSE
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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// synopsys translate_off
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$display(" WBMUX: muxin_b %h", muxin_b);
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$display(" WBMUX: muxin_b %h", muxin_b);
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// synopsys translate_on
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// synopsys translate_on
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`endif
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`endif
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end
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end
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2'b10: begin
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`OR1200_RFWBOP_SPRS: begin
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muxout = muxin_c;
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muxout = muxin_c;
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`ifdef OR1200_VERBOSE
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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// synopsys translate_off
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$display(" WBMUX: muxin_c %h", muxin_c);
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$display(" WBMUX: muxin_c %h", muxin_c);
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// synopsys translate_on
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// synopsys translate_on
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`endif
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`endif
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end
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end
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2'b11: begin
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`OR1200_RFWBOP_LR: begin
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muxout = muxin_d + 32'h8;
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muxout = muxin_d + 32'h8;
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`ifdef OR1200_VERBOSE
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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// synopsys translate_off
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$display(" WBMUX: muxin_d %h", muxin_d + 4'h8);
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$display(" WBMUX: muxin_d %h", muxin_d + 4'h8);
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// synopsys translate_on
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// synopsys translate_on
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`endif
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`endif
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end
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end
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`ifdef OR1200_FPU_IMPLEMENTED
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`OR1200_RFWBOP_FPU : begin
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muxout = muxin_e;
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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$display(" WBMUX: muxin_e %h", muxin_e);
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// synopsys translate_on
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`endif
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end
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`endif
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endcase
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endcase
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end
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end
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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