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Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_wbmux.v] - Diff between revs 358 and 364

Rev 358	Rev 364
Line 111...	Line 111...
`//`	`//`
`// Write-back multiplexer`	`// Write-back multiplexer`
`//`	`//`
`always @(muxin_a or muxin_b or muxin_c or muxin_d or muxin_e or rfwb_op) begin`	`always @(muxin_a or muxin_b or muxin_c or muxin_d or muxin_e or rfwb_op) begin`
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES	`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
case(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case infer_mux	casez(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case infer_mux
`else	`else
case(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case	casez(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case
`endif	`endif
`OR1200_RFWBOP_ALU: muxout = muxin_a;	`OR1200_RFWBOP_ALU: muxout = muxin_a;
`OR1200_RFWBOP_LSU: begin	`OR1200_RFWBOP_LSU: begin
`muxout = muxin_b;`	`muxout = muxin_b;`
`ifdef OR1200_VERBOSE	`ifdef OR1200_VERBOSE
Line 150...	Line 150...
`$display(" WBMUX: muxin_e %h", muxin_e);`	`$display(" WBMUX: muxin_e %h", muxin_e);`
`// synopsys translate_on`	`// synopsys translate_on`
`endif	`endif
`end`	`end`
`endif	`endif
	`default : begin`
	`muxout = 0;`
	`end`

`endcase`	`endcase`
`end`	`end`

`endmodule`	`endmodule`

`No newline at end of file`	`No newline at end of file`