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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
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//
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//
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// Write-back multiplexer
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// Write-back multiplexer
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//
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//
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always @(muxin_a or muxin_b or muxin_c or muxin_d or muxin_e or rfwb_op) begin
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always @(muxin_a or muxin_b or muxin_c or muxin_d or muxin_e or rfwb_op) begin
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`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
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`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
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case(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case infer_mux
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casez(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case infer_mux
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`else
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`else
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case(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case
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casez(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case
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`endif
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`endif
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`OR1200_RFWBOP_ALU: muxout = muxin_a;
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`OR1200_RFWBOP_ALU: muxout = muxin_a;
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`OR1200_RFWBOP_LSU: begin
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`OR1200_RFWBOP_LSU: begin
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muxout = muxin_b;
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muxout = muxin_b;
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`ifdef OR1200_VERBOSE
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`ifdef OR1200_VERBOSE
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$display(" WBMUX: muxin_e %h", muxin_e);
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$display(" WBMUX: muxin_e %h", muxin_e);
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// synopsys translate_on
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// synopsys translate_on
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`endif
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`endif
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end
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end
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`endif
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`endif
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default : begin
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muxout = 0;
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end
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endcase
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endcase
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end
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end
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endmodule
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endmodule
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