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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
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//
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//
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// Registered output from the write-back multiplexer
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// Registered output from the write-back multiplexer
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//
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//
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always @(posedge clk or posedge rst) begin
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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if (rst) begin
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muxreg <= #1 32'd0;
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muxreg <= 32'd0;
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muxreg_valid <= #1 1'b0;
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muxreg_valid <= 1'b0;
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end
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end
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else if (!wb_freeze) begin
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else if (!wb_freeze) begin
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muxreg <= #1 muxout;
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muxreg <= muxout;
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muxreg_valid <= #1 rfwb_op[0];
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muxreg_valid <= rfwb_op[0];
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end
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end
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end
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end
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//
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//
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// Write-back multiplexer
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// Write-back multiplexer
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