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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_xcv_ram32x8d.v] - Diff between revs 10 and 142

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Rev 10 Rev 142
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// CVS Revision History
// CVS Revision History
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//
// $Log: not supported by cvs2svn $
// $Log: or1200_xcv_ram32x8d.v,v $
 
// Revision 2.0  2010/06/30 11:00:00  ORSoC
 
// No update 
 
//
 
// Revision 1.2  2002/07/14 22:17:17  lampret
 
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
 
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
//
// Revision 1.7  2001/10/21 17:57:16  lampret
// Revision 1.7  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.

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