OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1ksim/] [ChangeLog] - Diff between revs 134 and 143

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 134 Rev 143
Line 1... Line 1...
 
2010-06-31  Jeremy Bennett 
 
        * argtable2/argtable2.c (arg_print_formatted): Cast argument to
 
        * configure: Regenerated.
 
        * configure.ac: Version changed to current date.
 
        isspace to int (x2).
 
        * debug/rsp-server.c (rsp_remove_matchpoint)
 
        (rsp_insert_matchpoint): Don't cast pointer to enum. Invalidate
 
        instruction cache before writing.
 
        (rsp_write_mem, rsp_write_mem_bin): Invalidate caches before writing.
 
        * NEWS: Updated for new version
 
 
 
2010-06-29  Jeremy Bennett 
 
        * configure: Regenerated.
 
        * configure.ac: Version changed to current date.
 
        * cpu/or32/insnset.c : On exit, mark cpu as halted if this
 
        is library.
 
        * libtoplevel.c: Add definitions of GDB register numbers.
 
        (or1ksim_init): Initailize config.sim.is_library.
 
        (or1ksim_run): Distinguish between halting and hitting breakpoint,
 
        return if stalled/halted after cpu_cock ().
 
        (or1ksim_step, or1ksim_read_mem, or1ksim_write_mem)
 
        (or1ksim_read_reg, or1ksim_write_reg): New functions.
 
        * NEWS: Updated for new version
 
        * sim-config.c (init_defconfig): Initialize config.sim.is_library.
 
        * sim-config.h : Added field sim.is_library.
 
        : Added field cpu.halted.
 
 
2010-06-22  Jeremy Bennett 
2010-06-22  Jeremy Bennett 
        * configure: Regenerated.
        * configure: Regenerated.
        * configure.ac: Version changed to 0.4.0.
        * configure.ac: Version changed to 0.4.0.
        * NEWS: Updated for 0.4.0.
        * NEWS: Updated for 0.4.0.
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.