OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [cache/] [dcache-model.c] - Diff between revs 224 and 556

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 224 Rev 556
Line 37... Line 37...
#include "execute.h"
#include "execute.h"
#include "spr-defs.h"
#include "spr-defs.h"
#include "abstract.h"
#include "abstract.h"
#include "stats.h"
#include "stats.h"
#include "misc.h"
#include "misc.h"
 
#include "pcu.h"
 
 
/* Data cache */
/* Data cache */
 
 
struct dc_set
struct dc_set
{
{
Line 183... Line 183...
        if (dc[set].way[i].lru)
        if (dc[set].way[i].lru)
          dc[set].way[i].lru--;
          dc[set].way[i].lru--;
      dc[set].way[minway].lru = config.dc.ustates - 1;
      dc[set].way[minway].lru = config.dc.ustates - 1;
      runtime.sim.mem_cycles += config.dc.load_missdelay;
      runtime.sim.mem_cycles += config.dc.load_missdelay;
 
 
 
      if (config.pcu.enabled)
 
        pcu_count_event(SPR_PCMR_DCM);
 
 
 
 
      tmp =
      tmp =
        dc[set].way[minway].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
        dc[set].way[minway].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
      if (width == 4)
      if (width == 4)
        return tmp;
        return tmp;
      else if (width == 2)
      else if (width == 2)
Line 302... Line 306...
      for (i = 0; i < config.dc.nways; i++)
      for (i = 0; i < config.dc.nways; i++)
        if (dc[set].way[i].lru)
        if (dc[set].way[i].lru)
          dc[set].way[i].lru--;
          dc[set].way[i].lru--;
      dc[set].way[minway].lru = config.dc.ustates - 1;
      dc[set].way[minway].lru = config.dc.ustates - 1;
      runtime.sim.mem_cycles += config.dc.store_missdelay;
      runtime.sim.mem_cycles += config.dc.store_missdelay;
 
 
 
      if (config.pcu.enabled)
 
        pcu_count_event(SPR_PCMR_DCM);
 
 
    }
    }
}
}
 
 
/* First check if data is already in the cache and if it is:
/* First check if data is already in the cache and if it is:
    - invalidate block if way isn't locked
    - invalidate block if way isn't locked

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.