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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
[/] [openrisc/] [trunk/] [or1ksim/] [cache/] [dcache-model.c] - Diff between revs 224 and 556
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| Rev 224 |
Rev 556 |
| Line 37... |
Line 37... |
#include "execute.h"
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#include "execute.h"
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#include "spr-defs.h"
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#include "spr-defs.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "stats.h"
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#include "stats.h"
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#include "misc.h"
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#include "misc.h"
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#include "pcu.h"
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/* Data cache */
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/* Data cache */
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struct dc_set
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struct dc_set
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{
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{
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| Line 183... |
Line 183... |
if (dc[set].way[i].lru)
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if (dc[set].way[i].lru)
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dc[set].way[i].lru--;
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dc[set].way[i].lru--;
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dc[set].way[minway].lru = config.dc.ustates - 1;
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dc[set].way[minway].lru = config.dc.ustates - 1;
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runtime.sim.mem_cycles += config.dc.load_missdelay;
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runtime.sim.mem_cycles += config.dc.load_missdelay;
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if (config.pcu.enabled)
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pcu_count_event(SPR_PCMR_DCM);
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tmp =
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tmp =
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dc[set].way[minway].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
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dc[set].way[minway].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
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if (width == 4)
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if (width == 4)
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return tmp;
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return tmp;
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else if (width == 2)
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else if (width == 2)
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| Line 302... |
Line 306... |
for (i = 0; i < config.dc.nways; i++)
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for (i = 0; i < config.dc.nways; i++)
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if (dc[set].way[i].lru)
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if (dc[set].way[i].lru)
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dc[set].way[i].lru--;
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dc[set].way[i].lru--;
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dc[set].way[minway].lru = config.dc.ustates - 1;
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dc[set].way[minway].lru = config.dc.ustates - 1;
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runtime.sim.mem_cycles += config.dc.store_missdelay;
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runtime.sim.mem_cycles += config.dc.store_missdelay;
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if (config.pcu.enabled)
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pcu_count_event(SPR_PCMR_DCM);
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}
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}
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}
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}
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/* First check if data is already in the cache and if it is:
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/* First check if data is already in the cache and if it is:
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- invalidate block if way isn't locked
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- invalidate block if way isn't locked
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