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https://opencores.org/ocsvn/openrisc/openrisc/trunk
[/] [openrisc/] [trunk/] [or1ksim/] [cache/] [icache-model.c] - Diff between revs 224 and 556
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| Rev 224 |
Rev 556 |
| Line 43... |
Line 43... |
#include "spr-defs.h"
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#include "spr-defs.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "misc.h"
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#include "misc.h"
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#include "stats.h"
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#include "stats.h"
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#include "sim-cmd.h"
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#include "sim-cmd.h"
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#include "pcu.h"
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#define MAX_IC_SETS 1024
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#define MAX_IC_SETS 1024
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#define MAX_IC_WAYS 32
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#define MAX_IC_WAYS 32
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#define MIN_IC_BLOCK_SIZE 16
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#define MIN_IC_BLOCK_SIZE 16
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#define MAX_IC_BLOCK_SIZE 32
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#define MAX_IC_BLOCK_SIZE 32
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| Line 173... |
Line 173... |
fprintf (cur_area->log, "[%" PRIxADDR "] -> read %08" PRIx32 "\n",
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fprintf (cur_area->log, "[%" PRIxADDR "] -> read %08" PRIx32 "\n",
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fetchaddr, tmp);
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fetchaddr, tmp);
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}
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}
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runtime.sim.mem_cycles += ic->missdelay;
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runtime.sim.mem_cycles += ic->missdelay;
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if (config.pcu.enabled)
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pcu_count_event(SPR_PCMR_ICM);
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return *(uint32_t *) & ic->mem[way | (reload_addr & ic->block_offset_mask)];
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return *(uint32_t *) & ic->mem[way | (reload_addr & ic->block_offset_mask)];
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}
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}
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/* First check if data is already in the cache and if it is:
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/* First check if data is already in the cache and if it is:
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- invalidate block if way isn't locked
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- invalidate block if way isn't locked
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