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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
[/] [openrisc/] [trunk/] [or1ksim/] [cache/] [icache-model.c] - Diff between revs 19 and 83
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| Rev 19 |
Rev 83 |
| Line 224... |
Line 224... |
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/*!Enable or disable the instruction cache
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/*!Enable or disable the instruction cache
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Set the corresponding field in the UPR
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Set the corresponding fields in the UPR
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@param[in] val The value to use
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@param[in] val The value to use
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@param[in] dat The config data structure */
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@param[in] dat The config data structure */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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static void
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static void
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| Line 481... |
Line 481... |
{
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{
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fprintf (stderr, "OOM\n");
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fprintf (stderr, "OOM\n");
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exit (1);
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exit (1);
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}
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}
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/* Clear the cache data. John Alfredo's fix for using 0 (which is a
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valid tag), so we now use -1 */
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memset (ic->mem, 0, size);
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memset (ic->mem, 0, size);
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memset (ic->lrus, 0, ic->nsets * ic->nways * sizeof (unsigned int));
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memset (ic->lrus, 0, ic->nsets * ic->nways * sizeof (unsigned int));
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memset (ic->tags, 0, ic->nsets * ic->nways * sizeof (oraddr_t));
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memset (ic->tags, -1, ic->nsets * ic->nways * sizeof (oraddr_t));
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}
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}
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else
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else
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{
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{
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ic->enabled = 0;
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ic->enabled = 0;
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}
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}
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