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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1ksim/] [cache/] [icache-model.c] - Diff between revs 224 and 556

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Rev 224 Rev 556
Line 43... Line 43...
#include "spr-defs.h"
#include "spr-defs.h"
#include "abstract.h"
#include "abstract.h"
#include "misc.h"
#include "misc.h"
#include "stats.h"
#include "stats.h"
#include "sim-cmd.h"
#include "sim-cmd.h"
 
#include "pcu.h"
 
 
#define MAX_IC_SETS        1024
#define MAX_IC_SETS        1024
#define MAX_IC_WAYS          32
#define MAX_IC_WAYS          32
#define MIN_IC_BLOCK_SIZE    16
#define MIN_IC_BLOCK_SIZE    16
#define MAX_IC_BLOCK_SIZE    32
#define MAX_IC_BLOCK_SIZE    32
Line 173... Line 173...
        fprintf (cur_area->log, "[%" PRIxADDR "] -> read %08" PRIx32 "\n",
        fprintf (cur_area->log, "[%" PRIxADDR "] -> read %08" PRIx32 "\n",
                 fetchaddr, tmp);
                 fetchaddr, tmp);
    }
    }
 
 
  runtime.sim.mem_cycles += ic->missdelay;
  runtime.sim.mem_cycles += ic->missdelay;
 
 
 
  if (config.pcu.enabled)
 
    pcu_count_event(SPR_PCMR_ICM);
 
 
 
 
  return *(uint32_t *) & ic->mem[way | (reload_addr & ic->block_offset_mask)];
  return *(uint32_t *) & ic->mem[way | (reload_addr & ic->block_offset_mask)];
}
}
 
 
/* First check if data is already in the cache and if it is:
/* First check if data is already in the cache and if it is:
    - invalidate block if way isn't locked
    - invalidate block if way isn't locked

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