| Line 45... |
Line 45... |
#include "labels.h"
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#include "labels.h"
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#include "opcode/or32.h"
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#include "opcode/or32.h"
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#include "dmmu.h"
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#include "dmmu.h"
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#include "immu.h"
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#include "immu.h"
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#include "execute.h"
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#include "execute.h"
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#include "pcu.h"
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/*! Global temporary variable to increase speed. */
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/*! Global temporary variable to increase speed. */
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struct dev_memarea *cur_area;
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struct dev_memarea *cur_area;
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/* Glboal variables set by MMU if cache inhibit bit is set for current
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/* Glboal variables set by MMU if cache inhibit bit is set for current
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| Line 484... |
Line 485... |
{
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{
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except_handle (EXCEPT_ALIGN, memaddr);
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except_handle (EXCEPT_ALIGN, memaddr);
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return 0;
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return 0;
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}
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}
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if (config.debug.enabled)
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*breakpoint += check_debug_unit (DebugLoadAddress, memaddr); /* 28/05/01 CZ */
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phys_memaddr = dmmu_translate (memaddr, 0);
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phys_memaddr = dmmu_translate (memaddr, 0);
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if (except_pending)
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if (except_pending)
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return 0;
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return 0;
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if (config.pcu.enabled)
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pcu_count_event(SPR_PCMR_LA);
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if (config.debug.enabled)
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*breakpoint += check_debug_unit (DebugLoadAddress, memaddr);
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if (config.dc.enabled)
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if (config.dc.enabled)
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temp = dc_simulate_read (phys_memaddr, memaddr, 4);
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temp = dc_simulate_read (phys_memaddr, memaddr, 4);
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else
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else
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temp = evalsim_mem32 (phys_memaddr, memaddr);
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temp = evalsim_mem32 (phys_memaddr, memaddr);
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if (config.debug.enabled)
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if (config.debug.enabled)
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*breakpoint += check_debug_unit (DebugLoadData, temp); /* MM170901 */
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*breakpoint += check_debug_unit (DebugLoadData, temp);
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return temp;
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return temp;
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}
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}
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/* for simulator accesses, the ones that cpu wouldn't do
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/* for simulator accesses, the ones that cpu wouldn't do
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| Line 562... |
Line 566... |
return 0;
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return 0;
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if (config.debug.enabled)
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if (config.debug.enabled)
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*breakpoint += check_debug_unit (DebugInstructionFetch, memaddr);
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*breakpoint += check_debug_unit (DebugInstructionFetch, memaddr);
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if (config.pcu.enabled)
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pcu_count_event(SPR_PCMR_IF);
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if ((NULL != ic_state) && ic_state->enabled)
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if ((NULL != ic_state) && ic_state->enabled)
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temp = ic_simulate_fetch (phys_memaddr, memaddr);
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temp = ic_simulate_fetch (phys_memaddr, memaddr);
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else
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else
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temp = evalsim_mem32 (phys_memaddr, memaddr);
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temp = evalsim_mem32 (phys_memaddr, memaddr);
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| Line 591... |
Line 598... |
{
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{
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except_handle (EXCEPT_ALIGN, memaddr);
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except_handle (EXCEPT_ALIGN, memaddr);
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return 0;
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return 0;
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}
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}
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if (config.debug.enabled)
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*breakpoint += check_debug_unit (DebugLoadAddress, memaddr); /* 28/05/01 CZ */
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phys_memaddr = dmmu_translate (memaddr, 0);
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phys_memaddr = dmmu_translate (memaddr, 0);
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if (except_pending)
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if (except_pending)
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return 0;
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return 0;
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if (config.pcu.enabled)
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pcu_count_event(SPR_PCMR_LA);
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if (config.debug.enabled)
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*breakpoint += check_debug_unit (DebugLoadAddress, memaddr);
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if (config.dc.enabled)
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if (config.dc.enabled)
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temp = dc_simulate_read (phys_memaddr, memaddr, 2);
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temp = dc_simulate_read (phys_memaddr, memaddr, 2);
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else
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else
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temp = evalsim_mem16 (phys_memaddr, memaddr);
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temp = evalsim_mem16 (phys_memaddr, memaddr);
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if (config.debug.enabled)
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if (config.debug.enabled)
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*breakpoint += check_debug_unit (DebugLoadData, temp); /* MM170901 */
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*breakpoint += check_debug_unit (DebugLoadData, temp);
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return temp;
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return temp;
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}
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}
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/* for simulator accesses, the ones that cpu wouldn't do
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/* for simulator accesses, the ones that cpu wouldn't do
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| Line 659... |
Line 669... |
oraddr_t phys_memaddr;
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oraddr_t phys_memaddr;
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if (config.sim.mprofile)
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if (config.sim.mprofile)
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mprofile (memaddr, MPROF_8 | MPROF_READ);
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mprofile (memaddr, MPROF_8 | MPROF_READ);
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if (config.debug.enabled)
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*breakpoint += check_debug_unit (DebugLoadAddress, memaddr); /* 28/05/01 CZ */
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phys_memaddr = dmmu_translate (memaddr, 0);
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phys_memaddr = dmmu_translate (memaddr, 0);
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if (except_pending)
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if (except_pending)
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return 0;
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return 0;
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if (config.pcu.enabled)
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pcu_count_event(SPR_PCMR_LA);
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if (config.debug.enabled)
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*breakpoint += check_debug_unit (DebugLoadAddress, memaddr);
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if (config.dc.enabled)
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if (config.dc.enabled)
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temp = dc_simulate_read (phys_memaddr, memaddr, 1);
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temp = dc_simulate_read (phys_memaddr, memaddr, 1);
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else
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else
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temp = evalsim_mem8 (phys_memaddr, memaddr);
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temp = evalsim_mem8 (phys_memaddr, memaddr);
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if (config.debug.enabled)
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if (config.debug.enabled)
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*breakpoint += check_debug_unit (DebugLoadData, temp); /* MM170901 */
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*breakpoint += check_debug_unit (DebugLoadData, temp);
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return temp;
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return temp;
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}
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}
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/* for simulator accesses, the ones that cpu wouldn't do
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/* for simulator accesses, the ones that cpu wouldn't do
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*
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*
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| Line 819... |
Line 832... |
phys_memaddr = dmmu_translate (memaddr, 1);;
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phys_memaddr = dmmu_translate (memaddr, 1);;
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/* If we produced exception don't set anything */
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/* If we produced exception don't set anything */
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if (except_pending)
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if (except_pending)
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return;
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return;
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if (config.pcu.enabled)
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pcu_count_event(SPR_PCMR_SA);
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if (config.debug.enabled)
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if (config.debug.enabled)
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{
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{
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*breakpoint += check_debug_unit (DebugStoreAddress, memaddr); /* 28/05/01 CZ */
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*breakpoint += check_debug_unit (DebugStoreAddress, memaddr); /* 28/05/01 CZ */
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*breakpoint += check_debug_unit (DebugStoreData, value);
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*breakpoint += check_debug_unit (DebugStoreData, value);
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}
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}
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| Line 900... |
Line 916... |
phys_memaddr = dmmu_translate (memaddr, 1);;
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phys_memaddr = dmmu_translate (memaddr, 1);;
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/* If we produced exception don't set anything */
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/* If we produced exception don't set anything */
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if (except_pending)
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if (except_pending)
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return;
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return;
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if (config.pcu.enabled)
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pcu_count_event(SPR_PCMR_SA);
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if (config.debug.enabled)
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if (config.debug.enabled)
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{
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{
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*breakpoint += check_debug_unit (DebugStoreAddress, memaddr); /* 28/05/01 CZ */
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*breakpoint += check_debug_unit (DebugStoreAddress, memaddr); /* 28/05/01 CZ */
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*breakpoint += check_debug_unit (DebugStoreData, value);
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*breakpoint += check_debug_unit (DebugStoreData, value);
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}
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}
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| Line 975... |
Line 994... |
phys_memaddr = dmmu_translate (memaddr, 1);;
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phys_memaddr = dmmu_translate (memaddr, 1);;
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/* If we produced exception don't set anything */
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/* If we produced exception don't set anything */
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if (except_pending)
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if (except_pending)
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return;
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return;
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if (config.pcu.enabled)
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pcu_count_event(SPR_PCMR_SA);
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if (config.debug.enabled)
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if (config.debug.enabled)
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{
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{
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*breakpoint += check_debug_unit (DebugStoreAddress, memaddr); /* 28/05/01 CZ */
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*breakpoint += check_debug_unit (DebugStoreAddress, memaddr); /* 28/05/01 CZ */
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*breakpoint += check_debug_unit (DebugStoreData, value);
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*breakpoint += check_debug_unit (DebugStoreData, value);
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}
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}
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