URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [common/] [abstract.c] - Diff between revs 420 and 458

Rev 420	Rev 458
Line 1251...	Line 1251...
`if (index >= 0)`	`if (index >= 0)`
`{`	`{`
`or1ksim_disassemble_trace_index (insn, index);`	`or1ksim_disassemble_trace_index (insn, index);`
`PRINTF ("%-24s", or1ksim_disassembled);`	`PRINTF ("%-24s", or1ksim_disassembled);`

`/* Put either the register assignment, or store */`	`/* Put either the register assignment, SPR value, or store */`
`if (-1 != trace_dest_reg)`	`if (-1 != trace_dest_spr)`
	`{`
	`PRINTF ("SPR[%04x] = %08x", (trace_dest_spr \|`
	`evalsim_reg (trace_dest_reg)),`
	`cpu_state.sprs[(trace_dest_spr \|`
	`evalsim_reg (trace_dest_reg))]);`

	`}`
	`else if (-1 != trace_dest_reg)`
`{`	`{`
`PRINTF ("r%-2u = %" PRIxREG "", trace_dest_reg,`	`PRINTF ("r%-2u = %" PRIxREG "", trace_dest_reg,`
`evalsim_reg (trace_dest_reg));`	`evalsim_reg (trace_dest_reg));`
`}`	`}`
`else`	`else`
Line 1290...	Line 1298...
`PRINTF (" ");`	`PRINTF (" ");`
`break;`	`break;`
`}`	`}`
`}`	`}`


`/* Print the flag */`	`/* Print the flag */`
`PRINTF (" flag: %u\n", cpu_state.sprs[SPR_SR] & SPR_SR_F ? 1 : 0);`	`PRINTF (" flag: %u\n", cpu_state.sprs[SPR_SR] & SPR_SR_F ? 1 : 0);`

`}`	`}`
`else`	`else`