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[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [common/] [abstract.c] - Diff between revs 458 and 472

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Rev 458 Rev 472
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/*!Trace the current instr to output
/*!Trace the current instr to output
 
 
   This is a simpler form of disassemble_memory for GDB instruction tracing.
   This is a simpler form of disassemble_memory for GDB instruction tracing.
 
 
   Output format is symbolic disassembly, one instruction per line. Start each
   Output format is symbolic disassembly, one instruction per line. Start each
   line with its hex address. At the end print the value of any destination
   line with a flag to indicate supervisor or user mode then its hex address
   register, the flag and the number of cycles executed.
   (physical and/or virtual in that order). At the end print the value of any
 
   destination register, the flag and the number of cycles executed.
 
 
   There are all sorts of ways to trip this up, but they are unlikely. The
   There are all sorts of ways to trip this up, but they are unlikely. The
   validity of a memory area is taken from the address of the start of a line
   validity of a memory area is taken from the address of the start of a line
   to be printed, so assumes the following 3 bytes are present. This could be
   to be printed, so assumes the following 3 bytes are present. This could be
   fooled by ridiculous memory declarations.
   fooled by ridiculous memory declarations.
 
 
   @param[in] addr  Address of the instruction to trace                     */
   @param[in] phyaddr   Physical address of the instruction to trace
 
   @param[in] virtaddr  Virtual address of the instruction to trace
 
   @param[in] insn      The instruction just fetched and possibly executed.  */
/*---------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
void
void
disassemble_instr (oraddr_t addr)
disassemble_instr (oraddr_t  phyaddr,
 
                   oraddr_t  virtaddr,
 
                   uint32_t  insn)
{
{
  PRINTF ("%" PRIxADDR ": ", addr);
  /* Log whether we are supervisor mode */
 
  printf ("%c ",
 
          (SPR_SR_SM == (cpu_state.sprs[SPR_SR] & SPR_SR_SM)) ? 'S' : 'U');
 
 
  if (verify_memoryarea (addr))
  /* The address */
 
  if (runtime.sim.trace_phy)
    {
    {
      uint32_t insn  = eval_direct32 (addr, 0, 0);
      PRINTF ("%" PRIxADDR ": ", phyaddr);
 
    }
 
 
 
  if (runtime.sim.trace_virt)
 
    {
 
      PRINTF ("%" PRIxADDR ": ", virtaddr);
 
    }
 
 
 
  /* The instruction details */
      int      index = or1ksim_insn_decode (insn);
      int      index = or1ksim_insn_decode (insn);
 
 
      PRINTF ("%08" PRIx32 " ", insn);
      PRINTF ("%08" PRIx32 " ", insn);
 
 
      if (index >= 0)
      if (index >= 0)
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        }
        }
      else
      else
        {
        {
          PRINTF ("<invalid>\n");
          PRINTF ("<invalid>\n");
        }
        }
    }
 
  else
 
    {
 
      /* Not a valid memory area. Print Xs as required */
 
      PRINTF ("XXXXXXXX\n");
 
    }
 
}       /* disassemble_instr() */
}       /* disassemble_instr() */
 
 
 
 
/* Closes files, etc. */
/* Closes files, etc. */
 
 

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