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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [common/] [abstract.c] - Diff between revs 552 and 556

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Rev 552 Rev 556
Line 45... Line 45...
#include "labels.h"
#include "labels.h"
#include "opcode/or32.h"
#include "opcode/or32.h"
#include "dmmu.h"
#include "dmmu.h"
#include "immu.h"
#include "immu.h"
#include "execute.h"
#include "execute.h"
 
#include "pcu.h"
 
 
/*! Global temporary variable to increase speed.  */
/*! Global temporary variable to increase speed.  */
struct dev_memarea *cur_area;
struct dev_memarea *cur_area;
 
 
/* Glboal variables set by MMU if cache inhibit bit is set for current
/* Glboal variables set by MMU if cache inhibit bit is set for current
Line 484... Line 485...
    {
    {
      except_handle (EXCEPT_ALIGN, memaddr);
      except_handle (EXCEPT_ALIGN, memaddr);
      return 0;
      return 0;
    }
    }
 
 
  if (config.debug.enabled)
 
    *breakpoint += check_debug_unit (DebugLoadAddress, memaddr);        /* 28/05/01 CZ */
 
 
 
  phys_memaddr = dmmu_translate (memaddr, 0);
  phys_memaddr = dmmu_translate (memaddr, 0);
  if (except_pending)
  if (except_pending)
    return 0;
    return 0;
 
 
 
  if (config.pcu.enabled)
 
    pcu_count_event(SPR_PCMR_LA);
 
 
 
  if (config.debug.enabled)
 
    *breakpoint += check_debug_unit (DebugLoadAddress, memaddr);
 
 
  if (config.dc.enabled)
  if (config.dc.enabled)
    temp = dc_simulate_read (phys_memaddr, memaddr, 4);
    temp = dc_simulate_read (phys_memaddr, memaddr, 4);
  else
  else
    temp = evalsim_mem32 (phys_memaddr, memaddr);
    temp = evalsim_mem32 (phys_memaddr, memaddr);
 
 
  if (config.debug.enabled)
  if (config.debug.enabled)
    *breakpoint += check_debug_unit (DebugLoadData, temp);      /* MM170901 */
    *breakpoint += check_debug_unit (DebugLoadData, temp);
 
 
  return temp;
  return temp;
}
}
 
 
/* for simulator accesses, the ones that cpu wouldn't do
/* for simulator accesses, the ones that cpu wouldn't do
Line 562... Line 566...
    return 0;
    return 0;
 
 
  if (config.debug.enabled)
  if (config.debug.enabled)
    *breakpoint += check_debug_unit (DebugInstructionFetch, memaddr);
    *breakpoint += check_debug_unit (DebugInstructionFetch, memaddr);
 
 
 
  if (config.pcu.enabled)
 
    pcu_count_event(SPR_PCMR_IF);
 
 
  if ((NULL != ic_state) && ic_state->enabled)
  if ((NULL != ic_state) && ic_state->enabled)
    temp = ic_simulate_fetch (phys_memaddr, memaddr);
    temp = ic_simulate_fetch (phys_memaddr, memaddr);
  else
  else
    temp = evalsim_mem32 (phys_memaddr, memaddr);
    temp = evalsim_mem32 (phys_memaddr, memaddr);
 
 
Line 591... Line 598...
    {
    {
      except_handle (EXCEPT_ALIGN, memaddr);
      except_handle (EXCEPT_ALIGN, memaddr);
      return 0;
      return 0;
    }
    }
 
 
  if (config.debug.enabled)
 
    *breakpoint += check_debug_unit (DebugLoadAddress, memaddr);        /* 28/05/01 CZ */
 
 
 
  phys_memaddr = dmmu_translate (memaddr, 0);
  phys_memaddr = dmmu_translate (memaddr, 0);
  if (except_pending)
  if (except_pending)
    return 0;
    return 0;
 
 
 
  if (config.pcu.enabled)
 
    pcu_count_event(SPR_PCMR_LA);
 
 
 
  if (config.debug.enabled)
 
    *breakpoint += check_debug_unit (DebugLoadAddress, memaddr);
 
 
  if (config.dc.enabled)
  if (config.dc.enabled)
    temp = dc_simulate_read (phys_memaddr, memaddr, 2);
    temp = dc_simulate_read (phys_memaddr, memaddr, 2);
  else
  else
    temp = evalsim_mem16 (phys_memaddr, memaddr);
    temp = evalsim_mem16 (phys_memaddr, memaddr);
 
 
  if (config.debug.enabled)
  if (config.debug.enabled)
    *breakpoint += check_debug_unit (DebugLoadData, temp);      /* MM170901 */
    *breakpoint += check_debug_unit (DebugLoadData, temp);
 
 
  return temp;
  return temp;
}
}
 
 
/* for simulator accesses, the ones that cpu wouldn't do
/* for simulator accesses, the ones that cpu wouldn't do
Line 659... Line 669...
  oraddr_t phys_memaddr;
  oraddr_t phys_memaddr;
 
 
  if (config.sim.mprofile)
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_8 | MPROF_READ);
    mprofile (memaddr, MPROF_8 | MPROF_READ);
 
 
  if (config.debug.enabled)
 
    *breakpoint += check_debug_unit (DebugLoadAddress, memaddr);        /* 28/05/01 CZ */
 
 
 
  phys_memaddr = dmmu_translate (memaddr, 0);
  phys_memaddr = dmmu_translate (memaddr, 0);
  if (except_pending)
  if (except_pending)
    return 0;
    return 0;
 
 
 
  if (config.pcu.enabled)
 
    pcu_count_event(SPR_PCMR_LA);
 
 
 
  if (config.debug.enabled)
 
    *breakpoint += check_debug_unit (DebugLoadAddress, memaddr);
 
 
  if (config.dc.enabled)
  if (config.dc.enabled)
    temp = dc_simulate_read (phys_memaddr, memaddr, 1);
    temp = dc_simulate_read (phys_memaddr, memaddr, 1);
  else
  else
    temp = evalsim_mem8 (phys_memaddr, memaddr);
    temp = evalsim_mem8 (phys_memaddr, memaddr);
 
 
  if (config.debug.enabled)
  if (config.debug.enabled)
    *breakpoint += check_debug_unit (DebugLoadData, temp);      /* MM170901 */
    *breakpoint += check_debug_unit (DebugLoadData, temp);
  return temp;
  return temp;
}
}
 
 
/* for simulator accesses, the ones that cpu wouldn't do
/* for simulator accesses, the ones that cpu wouldn't do
 *
 *
Line 819... Line 832...
  phys_memaddr = dmmu_translate (memaddr, 1);;
  phys_memaddr = dmmu_translate (memaddr, 1);;
  /* If we produced exception don't set anything */
  /* If we produced exception don't set anything */
  if (except_pending)
  if (except_pending)
    return;
    return;
 
 
 
  if (config.pcu.enabled)
 
    pcu_count_event(SPR_PCMR_SA);
 
 
  if (config.debug.enabled)
  if (config.debug.enabled)
    {
    {
      *breakpoint += check_debug_unit (DebugStoreAddress, memaddr);     /* 28/05/01 CZ */
      *breakpoint += check_debug_unit (DebugStoreAddress, memaddr);     /* 28/05/01 CZ */
      *breakpoint += check_debug_unit (DebugStoreData, value);
      *breakpoint += check_debug_unit (DebugStoreData, value);
    }
    }
Line 900... Line 916...
  phys_memaddr = dmmu_translate (memaddr, 1);;
  phys_memaddr = dmmu_translate (memaddr, 1);;
  /* If we produced exception don't set anything */
  /* If we produced exception don't set anything */
  if (except_pending)
  if (except_pending)
    return;
    return;
 
 
 
  if (config.pcu.enabled)
 
    pcu_count_event(SPR_PCMR_SA);
 
 
  if (config.debug.enabled)
  if (config.debug.enabled)
    {
    {
      *breakpoint += check_debug_unit (DebugStoreAddress, memaddr);     /* 28/05/01 CZ */
      *breakpoint += check_debug_unit (DebugStoreAddress, memaddr);     /* 28/05/01 CZ */
      *breakpoint += check_debug_unit (DebugStoreData, value);
      *breakpoint += check_debug_unit (DebugStoreData, value);
    }
    }
Line 975... Line 994...
  phys_memaddr = dmmu_translate (memaddr, 1);;
  phys_memaddr = dmmu_translate (memaddr, 1);;
  /* If we produced exception don't set anything */
  /* If we produced exception don't set anything */
  if (except_pending)
  if (except_pending)
    return;
    return;
 
 
 
  if (config.pcu.enabled)
 
    pcu_count_event(SPR_PCMR_SA);
 
 
  if (config.debug.enabled)
  if (config.debug.enabled)
    {
    {
      *breakpoint += check_debug_unit (DebugStoreAddress, memaddr);     /* 28/05/01 CZ */
      *breakpoint += check_debug_unit (DebugStoreAddress, memaddr);     /* 28/05/01 CZ */
      *breakpoint += check_debug_unit (DebugStoreData, value);
      *breakpoint += check_debug_unit (DebugStoreData, value);
    }
    }

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