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[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [common/] [abstract.c] - Diff between revs 230 and 420

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Rev 230 Rev 420
Line 44... Line 44...
#include "dcache-model.h"
#include "dcache-model.h"
#include "labels.h"
#include "labels.h"
#include "opcode/or32.h"
#include "opcode/or32.h"
#include "dmmu.h"
#include "dmmu.h"
#include "immu.h"
#include "immu.h"
 
#include "execute.h"
 
 
#if DYNAMIC_EXECUTION
#if DYNAMIC_EXECUTION
#include "dyn-rec.h"
#include "dyn-rec.h"
#endif
#endif
 
 
Line 1217... Line 1218...
        }
        }
    }
    }
}                               /* disassemble_memory() */
}                               /* disassemble_memory() */
 
 
 
 
 
/*---------------------------------------------------------------------------*/
 
/*!Trace the current instr to output
 
 
 
   This is a simpler form of disassemble_memory for GDB instruction tracing.
 
 
 
   Output format is symbolic disassembly, one instruction per line. Start each
 
   line with its hex address. At the end print the value of any destination
 
   register, the flag and the number of cycles executed.
 
 
 
   There are all sorts of ways to trip this up, but they are unlikely. The
 
   validity of a memory area is taken from the address of the start of a line
 
   to be printed, so assumes the following 3 bytes are present. This could be
 
   fooled by ridiculous memory declarations.
 
 
 
   @param[in] addr  Address of the instruction to trace                     */
 
/*---------------------------------------------------------------------------*/
 
void
 
disassemble_instr (oraddr_t addr)
 
{
 
  PRINTF ("%" PRIxADDR ": ", addr);
 
 
 
  if (verify_memoryarea (addr))
 
    {
 
      uint32_t insn  = eval_direct32 (addr, 0, 0);
 
      int      index = or1ksim_insn_decode (insn);
 
 
 
      PRINTF ("%08" PRIx32 " ", insn);
 
 
 
      if (index >= 0)
 
        {
 
          or1ksim_disassemble_trace_index (insn, index);
 
          PRINTF ("%-24s", or1ksim_disassembled);
 
 
 
          /* Put either the register assignment, or store */
 
          if (-1 != trace_dest_reg)
 
            {
 
              PRINTF ("r%-2u        = %" PRIxREG "", trace_dest_reg,
 
                       evalsim_reg (trace_dest_reg));
 
            }
 
          else
 
            {
 
              uorreg_t  store_val  = 0;
 
              oraddr_t  store_addr = 0;
 
 
 
              if (0 != trace_store_width)
 
                {
 
                  store_val  = evalsim_reg (trace_store_val_reg);
 
                  store_addr = evalsim_reg (trace_store_addr_reg) +
 
                               trace_store_imm;
 
                }
 
 
 
              switch (trace_store_width)
 
                {
 
                case 1:
 
                  PRINTF ("[%" PRIxADDR "] = %02x      ", store_addr,
 
                          store_val);
 
                  break;
 
 
 
                case 2:
 
                  PRINTF ("[%" PRIxADDR "] = %04x    ", store_addr, store_val);
 
                  break;
 
 
 
                case 4:
 
                  PRINTF ("[%" PRIxADDR "] = %08x", store_addr, store_val);
 
                  break;
 
 
 
                default:
 
                  PRINTF ("                     ");
 
                  break;
 
                }
 
            }
 
 
 
          /* Print the flag */
 
          PRINTF ("  flag: %u\n", cpu_state.sprs[SPR_SR] & SPR_SR_F ? 1 : 0);
 
 
 
        }
 
      else
 
        {
 
          PRINTF ("<invalid>\n");
 
        }
 
    }
 
  else
 
    {
 
      /* Not a valid memory area. Print Xs as required */
 
      PRINTF ("XXXXXXXX\n");
 
    }
 
}       /* disassemble_instr() */
 
 
 
 
/* Closes files, etc. */
/* Closes files, etc. */
 
 
void
void
done_memory_table ()
done_memory_table ()
{
{

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