URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [or1k/] [spr-defs.h] - Diff between revs 559 and 561

Rev 559	Rev 561
Line 584...	Line 584...

`/*`	`/*`
`* Bit definitions for Tick Timer Control Register`	`* Bit definitions for Tick Timer Control Register`
`*`	`*`
`*/`	`*/`
`#define SPR_TTCR_CNT 0x0fffffff /* Count, time period */`	`#define SPR_TTCR_CNT 0xffffffff /* Count, time period */`
`#define SPR_TTMR_TP 0x0fffffff /* Time period */`	`#define SPR_TTMR_TP 0x0fffffff /* Time period */`
`#define SPR_TTMR_IP 0x10000000 /* Interrupt Pending */`	`#define SPR_TTMR_IP 0x10000000 /* Interrupt Pending */`
`#define SPR_TTMR_IE 0x20000000 /* Interrupt Enable */`	`#define SPR_TTMR_IE 0x20000000 /* Interrupt Enable */`
`#define SPR_TTMR_DI 0x00000000 /* Disabled */`	`#define SPR_TTMR_DI 0x00000000 /* Disabled */`
`#define SPR_TTMR_RT 0x40000000 /* Restart tick */`	`#define SPR_TTMR_RT 0x40000000 /* Restart tick */`