URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [or1k/] [spr-defs.h] - Diff between revs 82 and 224

Rev 82	Rev 224
Line 92...	Line 92...
`#define SPR_EPCR_LAST (SPRGROUP_SYS + 47) /* CZ 21/06/01 */`	`#define SPR_EPCR_LAST (SPRGROUP_SYS + 47) /* CZ 21/06/01 */`
`#define SPR_EEAR_BASE (SPRGROUP_SYS + 48)`	`#define SPR_EEAR_BASE (SPRGROUP_SYS + 48)`
`#define SPR_EEAR_LAST (SPRGROUP_SYS + 63)`	`#define SPR_EEAR_LAST (SPRGROUP_SYS + 63)`
`#define SPR_ESR_BASE (SPRGROUP_SYS + 64)`	`#define SPR_ESR_BASE (SPRGROUP_SYS + 64)`
`#define SPR_ESR_LAST (SPRGROUP_SYS + 79)`	`#define SPR_ESR_LAST (SPRGROUP_SYS + 79)`
	`#define SPR_GPR_BASE (SPRGROUP_SYS + 1024)`

`/* Data MMU group */`	`/* Data MMU group */`
`#define SPR_DMMUCR (SPRGROUP_DMMU + 0)`	`#define SPR_DMMUCR (SPRGROUP_DMMU + 0)`
`#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)`	`#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)`
`#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)`	`#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)`