| Line 72... |
Line 72... |
#define SPRGROUP_D (6<< MAX_SPRS_PER_GRP_BITS)
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#define SPRGROUP_D (6<< MAX_SPRS_PER_GRP_BITS)
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#define SPRGROUP_PC (7<< MAX_SPRS_PER_GRP_BITS)
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#define SPRGROUP_PC (7<< MAX_SPRS_PER_GRP_BITS)
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#define SPRGROUP_PM (8<< MAX_SPRS_PER_GRP_BITS)
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#define SPRGROUP_PM (8<< MAX_SPRS_PER_GRP_BITS)
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#define SPRGROUP_PIC (9<< MAX_SPRS_PER_GRP_BITS)
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#define SPRGROUP_PIC (9<< MAX_SPRS_PER_GRP_BITS)
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#define SPRGROUP_TT (10<< MAX_SPRS_PER_GRP_BITS)
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#define SPRGROUP_TT (10<< MAX_SPRS_PER_GRP_BITS)
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#define SPRGROUP_FP (11<< MAX_SPRS_PER_GRP_BITS)
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/* System control and status group */
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/* System control and status group */
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#define SPR_VR (SPRGROUP_SYS + 0)
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#define SPR_VR (SPRGROUP_SYS + 0)
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#define SPR_UPR (SPRGROUP_SYS + 1)
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#define SPR_UPR (SPRGROUP_SYS + 1)
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#define SPR_CPUCFGR (SPRGROUP_SYS + 2)
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#define SPR_CPUCFGR (SPRGROUP_SYS + 2)
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Line 87... |
#define SPR_DCFGR (SPRGROUP_SYS + 7)
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#define SPR_DCFGR (SPRGROUP_SYS + 7)
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#define SPR_PCCFGR (SPRGROUP_SYS + 8)
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#define SPR_PCCFGR (SPRGROUP_SYS + 8)
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#define SPR_NPC (SPRGROUP_SYS + 16) /* CZ 21/06/01 */
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#define SPR_NPC (SPRGROUP_SYS + 16) /* CZ 21/06/01 */
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#define SPR_SR (SPRGROUP_SYS + 17) /* CZ 21/06/01 */
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#define SPR_SR (SPRGROUP_SYS + 17) /* CZ 21/06/01 */
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#define SPR_PPC (SPRGROUP_SYS + 18) /* CZ 21/06/01 */
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#define SPR_PPC (SPRGROUP_SYS + 18) /* CZ 21/06/01 */
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#define SPR_FPCSR (SPRGROUP_SYS + 20) /* CZ 21/06/01 */
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#define SPR_EPCR_BASE (SPRGROUP_SYS + 32) /* CZ 21/06/01 */
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#define SPR_EPCR_BASE (SPRGROUP_SYS + 32) /* CZ 21/06/01 */
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#define SPR_EPCR_LAST (SPRGROUP_SYS + 47) /* CZ 21/06/01 */
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#define SPR_EPCR_LAST (SPRGROUP_SYS + 47) /* CZ 21/06/01 */
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#define SPR_EEAR_BASE (SPRGROUP_SYS + 48)
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#define SPR_EEAR_BASE (SPRGROUP_SYS + 48)
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#define SPR_EEAR_LAST (SPRGROUP_SYS + 63)
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#define SPR_EEAR_LAST (SPRGROUP_SYS + 63)
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#define SPR_ESR_BASE (SPRGROUP_SYS + 64)
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#define SPR_ESR_BASE (SPRGROUP_SYS + 64)
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Line 592... |
#define SPR_TTMR_SR 0x80000000 /* Single run */
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#define SPR_TTMR_SR 0x80000000 /* Single run */
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#define SPR_TTMR_CR 0xc0000000 /* Continuous run */
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#define SPR_TTMR_CR 0xc0000000 /* Continuous run */
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#define SPR_TTMR_M 0xc0000000 /* Tick mode */
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#define SPR_TTMR_M 0xc0000000 /* Tick mode */
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/*
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/*
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* Bit definitions for the FP Control Status Register
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*
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*/
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#define SPR_FPCSR_FPEE 0x00000001 /* Floating Point Exception Enable */
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#define SPR_FPCSR_RM 0x00000006 /* Rounding Mode */
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#define SPR_FPCSR_OVF 0x00000008 /* Overflow Flag */
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#define SPR_FPCSR_UNF 0x00000010 /* Underflow Flag */
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#define SPR_FPCSR_SNF 0x00000020 /* SNAN Flag */
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#define SPR_FPCSR_QNF 0x00000040 /* QNAN Flag */
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#define SPR_FPCSR_ZF 0x00000080 /* Zero Flag */
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#define SPR_FPCSR_IXF 0x00000100 /* Inexact Flag */
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#define SPR_FPCSR_IVF 0x00000200 /* Invalid Flag */
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#define SPR_FPCSR_INF 0x00000400 /* Infinity Flag */
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#define SPR_FPCSR_DZF 0x00000800 /* Divide By Zero Flag */
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#define SPR_FPCSR_ALLF (SPR_FPCSR_OVF | SPR_FPCSR_UNF | SPR_FPCSR_SNF | \
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SPR_FPCSR_QNF | SPR_FPCSR_ZF | SPR_FPCSR_IXF | \
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SPR_FPCSR_IVF | SPR_FPCSR_INF | SPR_FPCSR_DZF)
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#define FPCSR_RM_RN (0<<1)
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#define FPCSR_RM_RZ (1<<1)
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#define FPCSR_RM_RIP (2<<1)
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#define FPCSR_RM_RIN (3<<1)
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/*
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* l.nop constants
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* l.nop constants
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*
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*
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*/
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*/
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#define NOP_NOP 0x0000 /* Normal nop instruction */
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#define NOP_NOP 0x0000 /* Normal nop instruction */
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#define NOP_EXIT 0x0001 /* End of simulation */
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#define NOP_EXIT 0x0001 /* End of simulation */
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