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https://opencores.org/ocsvn/openrisc/openrisc/trunk
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}
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}
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}
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}
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break;
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break;
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case SPR_PICSR:
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case SPR_PICSR:
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if(!config.pic.edge_trigger)
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if(!config.pic.edge_trigger)
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/* When configured with level triggered interrupts we clear PICSR in PIC
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when IRQ goes low */
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cpu_state.sprs[SPR_PICSR] = prev_val;
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cpu_state.sprs[SPR_PICSR] = prev_val;
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break;
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break;
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case SPR_PICMR:
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case SPR_PICMR:
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if(cpu_state.sprs[SPR_SR] & SPR_SR_IEE)
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if(cpu_state.sprs[SPR_SR] & SPR_SR_IEE)
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pic_ints_en();
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pic_ints_en();
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