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[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [or1k/] [sprs.c] - Diff between revs 430 and 432

Rev 430	Rev 432
Line 157...	Line 157...
`/* When configured with level triggered interrupts we clear PICSR in PIC`	`/* When configured with level triggered interrupts we clear PICSR in PIC`
`when IRQ goes low */`	`when IRQ goes low */`
`cpu_state.sprs[SPR_PICSR] = prev_val;`	`cpu_state.sprs[SPR_PICSR] = prev_val;`
`break;`	`break;`
`case SPR_PICMR:`	`case SPR_PICMR:`
	`/* If we have non-maskable interrupts, then the bottom two bits are always`
	`one. */`
	`if (config.pic.use_nmi)`
	`{`
	`cpu_state.sprs[SPR_SR] \|= 0x00000003;`
	`}`

`if(cpu_state.sprs[SPR_SR] & SPR_SR_IEE)`	`if(cpu_state.sprs[SPR_SR] & SPR_SR_IEE)`
`pic_ints_en();`	`pic_ints_en();`
`break;`	`break;`
`case SPR_PMR:`	`case SPR_PMR:`
`/* PMR[SDF] and PMR[DCGE] are ignored completely. */`	`/* PMR[SDF] and PMR[DCGE] are ignored completely. */`