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[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [or1k/] [sprs.c] - Diff between revs 432 and 436

Rev 432	Rev 436
Line 153...	Line 153...
`}`	`}`
`break;`	`break;`
`case SPR_PICSR:`	`case SPR_PICSR:`
`if(!config.pic.edge_trigger)`	`if(!config.pic.edge_trigger)`
`/* When configured with level triggered interrupts we clear PICSR in PIC`	`/* When configured with level triggered interrupts we clear PICSR in PIC`
`when IRQ goes low */`	`peripheral model when incoming IRQ goes low */`
`cpu_state.sprs[SPR_PICSR] = prev_val;`	`cpu_state.sprs[SPR_PICSR] = prev_val;`
`break;`	`break;`
`case SPR_PICMR:`	`case SPR_PICMR:`
`/* If we have non-maskable interrupts, then the bottom two bits are always`	`/* If we have non-maskable interrupts, then the bottom two bits are always`
`one. */`	`one. */`